mb/intel/adlrvp: Configure GPIOs for ADLRVP-M

List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP

TEST=Able to build ADL-M

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>

3 files changed, 105 insertions, 1 deletions

diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index 75c8cf8e20..609bed5e5e 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -4,7 +4,13 @@ subdirs-y += spd
 
 bootblock-y += bootblock.c
 bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y)
+bootblock-y += early_gpio_m.c
+ramstage-y += gpio_m.c
+else
 bootblock-y += early_gpio.c
+ramstage-y += gpio.c
+endif
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
@@ -17,7 +23,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
-ramstage-y += gpio.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
new file mode 100644
index 0000000000..c2570045eb
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_E5, 0, PLTRST),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
new file mode 100644
index 0000000000..9eef27fd78
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* H4  : I2C0 SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H6  : I2C1 SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* B16 : I2C5 SDA */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+
+	/* H5  : I2C0 SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H7  : I2C1 SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* B17 : I2C5 SCL */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+	/* C5  : WWAN_PERST_N */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+	/* E5  : WWAN_PERST# */
+	PAD_CFG_GPO(GPP_E5, 1, PLTRST),
+	/* D15 : WWAN_DISABLE_N */
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	/* D9  : WWAN_FCP_POWER_OFF_N */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+
+	/* D10 : PCH_SSD_PWR_EN */
+	PAD_CFG_GPO(GPP_D10, 1, PLTRST),
+	/* H0  : PCH_SSD_RST# */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* D16 : CPU_SSD_PWR_EN */
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	/* H13 : CPU_SSD_RST# */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+
+	/* DDP1/2/A/B  CTRLCLK and CTRLDATA pins */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+
+	/* HPD_1 (E14) and HPD_2 (A18) pins */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+
+	/* GPIO pin for PCIE SRCCLKREQB */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+
+};
+
+void variant_configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}