diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
140 files changed, 1214 insertions, 1215 deletions
diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex index 97fec9dd37..c11e62219d 100644 --- a/Documentation/RFC/config.tex +++ b/Documentation/RFC/config.tex @@ -119,8 +119,8 @@ addaction ::= 'addaction' PATH ``ACTION'' statement ::= option | default - | cpu - | arch + | cpu + | arch | northbridge | southbridge | superio diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 1e0b5c826a..05f77950d9 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -232,7 +232,7 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) (fvih->Count * sizeof (FIRMWARE_VERSION_INFO))); size -= sizeof(SMBIOS_STRUCTURE); - printk(BIOS_DEBUG, "Display FSP Version Info HOB \n"); + printk(BIOS_DEBUG, "Display FSP Version Info HOB\n"); for (index = 0; index < fvih->Count; index++) { cnt = strlen(str_ptr); diff --git a/src/include/bootstate.h b/src/include/bootstate.h index c15cb308d7..edfabe553c 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -124,7 +124,7 @@ struct boot_state_callback { #if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE) #define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__) #define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC, -#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ +#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ do { \ bscb_->location = BOOT_STATE_CALLBACK_LOC; \ } while (0) diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index 5e7280a3cb..c78c508474 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/amd/amdfam10/root_complex device cpu_cluster 0 on chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on @@ -54,49 +54,49 @@ chip northbridge/amd/amdfam10/root_complex device i2c 53 on end end end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/bettong/acpi/gpe.asl +++ b/src/mainboard/amd/bettong/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 37257c42ff..505b519776 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index 0bcc9c16af..ba6a0fafcf 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 off end # PCIE P2P bridge 0x960b @@ -38,7 +38,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index b6a8e17a42..96dc819045 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -234,9 +234,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -832,7 +832,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -847,13 +847,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1020,7 +1020,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1043,19 +1043,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1067,7 +1067,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1084,7 +1084,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1115,7 +1115,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1125,7 +1125,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1477,7 +1477,7 @@ DefinitionBlock ( ) #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1607,7 +1607,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 0c26416e75..d4397b2372 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable port80 decoding and southbridge poweron init */ sb800_lpc_port80(); - inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ + inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ } post_code(0x30); diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl +++ b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl index 03d46dcf76..549adc00ec 100644 --- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl +++ b/src/mainboard/amd/db-ft3b-lc/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl index e713ad6688..6429bc604a 100644 --- a/src/mainboard/amd/gardenia/acpi/gpe.asl +++ b/src/mainboard/amd/gardenia/acpi/gpe.asl @@ -66,4 +66,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 2f22758712..30e6fdcb3c 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl index 0069aa9db2..47de049dbc 100644 --- a/src/mainboard/amd/inagua/acpi/sleep.asl +++ b/src/mainboard/amd/inagua/acpi/sleep.asl @@ -49,7 +49,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl index 299d4aa55c..6e9c701a26 100644 --- a/src/mainboard/amd/inagua/acpi/usb_oc.asl +++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl @@ -36,7 +36,7 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl index c5753eea51..297d9b47cb 100644 --- a/src/mainboard/amd/lamar/acpi/gpe.asl +++ b/src/mainboard/amd/lamar/acpi/gpe.asl @@ -70,4 +70,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl index 2d26a54f6c..f7edfb9119 100644 --- a/src/mainboard/amd/lamar/acpi/sleep.asl +++ b/src/mainboard/amd/lamar/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 5000b0c27c..dba1470f33 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index fe2c9869fe..57afc29547 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1520,7 +1520,7 @@ DefinitionBlock ( 0xF300 /* length */ ) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ @@ -1652,7 +1652,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index e70998921c..e2d02087cc 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl +++ b/src/mainboard/amd/olivehillplus/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index 03d46dcf76..549adc00ec 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 8e7840fad5..32d5a2a321 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl index 947a2f2d43..d516ccedb0 100644 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 2f22758712..30e6fdcb3c 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl index 0069aa9db2..47de049dbc 100644 --- a/src/mainboard/amd/persimmon/acpi/sleep.asl +++ b/src/mainboard/amd/persimmon/acpi/sleep.asl @@ -49,7 +49,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 8e7840fad5..32d5a2a321 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index 1dc590f484..9dd24e42b3 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 77fd875ada..06e33f728d 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 51128bb218..2151222033 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1521,7 +1521,7 @@ DefinitionBlock ( #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1655,7 +1655,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 44c1df69ba..5e112158c2 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -24,8 +24,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ADT7461_ADDRESS 0x4C +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -150,7 +150,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -162,7 +162,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index 2ce1dfd29e..2adfb27274 100644 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -13,56 +13,56 @@ # GNU General Public License for more details. # chip northbridge/amd/agesa/family12/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family12 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family12 # CPU side of HT root complex - chip northbridge/amd/agesa/family12 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics Bridge - device pci 1.1 on end # Audio Controller - device pci 2.0 on end # Root Port - device pci 3.0 on end # Root Port - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC + device cpu_cluster 0 on + chip cpu/amd/agesa/family12 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family12 # CPU side of HT root complex + chip northbridge/amd/agesa/family12 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics Bridge + device pci 1.1 on end # Audio Controller + device pci 2.0 on end # Root Port + device pci 3.0 on end # Root Port + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 + end #LPC device pci 14.4 on end # PCI bridge - device pci 14.5 on end # USB 2 + device pci 14.5 on end # USB 2 device pci 14.6 on end # Ethernet Controller device pci 14.7 on end # SD Flash Controller device pci 15.0 on end # PCIe PortA @@ -70,16 +70,16 @@ chip northbridge/amd/agesa/family12/root_complex device pci 15.2 on end # PCIe PortC device pci 15.3 on end # PCIe PortD register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb900 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex - end #domain + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family12/root_complex diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 0c55ff4c1b..4ee5fb4ad7 100644 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -676,7 +676,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -691,13 +691,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -766,7 +766,7 @@ DefinitionBlock ( } /* End Method(\_WAK) */ Scope(\_GPE) { /* Start Scope GPE */ - } /* End Scope GPE */ + } /* End Scope GPE */ /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 5a77dc0de0..e26052a734 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -75,7 +75,7 @@ void gpioEarlyInit(void) { StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B + if (StripInfo < boardRevC) { // for old board. Rev B Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 } diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl index 0afb841435..bde6fb628d 100644 --- a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -231,7 +231,7 @@ /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 2f1e86a14b..575715cf66 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -126,7 +126,7 @@ DefinitionBlock ( Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - } /* End Scope GPE */ + } /* End Scope GPE */ /* Root of the bus hierarchy */ Scope (\_SB) diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index cfbade68f2..f4e549b17f 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 56a6bdffd5..2809f0fe91 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -318,8 +318,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block */ if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); } #endif @@ -344,8 +344,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + outb(0x87, port); + outb(0x87, port); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb index 5bee5ae96a..bc9ad17c93 100644 --- a/src/mainboard/asus/p3b-f/devicetree.cb +++ b/src/mainboard/asus/p3b-f/devicetree.cb @@ -1,59 +1,59 @@ chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/slot_1 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end end diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01d7f..2bf3ca9c00 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -41,49 +41,49 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 Keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 Keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 43d14ede49..71fed875de 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -62,7 +62,7 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" - register "SerialIrqConfigSirqMode" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ @@ -226,17 +226,17 @@ chip soc/intel/skylake [7] = 1, \ }" register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoPci, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoPci, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" # PL2 override 25W diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 416906f03e..0c72c86ed5 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -237,7 +237,7 @@ chip northbridge/intel/gm45 device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index f03b87e6c0..6decf9bebb 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index b69b66c2fa..33b9368f50 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index a28c177572..3103762b0f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -158,7 +158,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 2a22d4e268..d9d9df5e14 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -10,12 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_dp_c_hotplug" = "0" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index aab647fa11..053b9d30cb 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -221,7 +221,7 @@ chip northbridge/intel/i945 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cb2d8f3b89..49e5933f5f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -126,7 +126,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end chip ec/lenovo/h8 @@ -166,7 +166,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21f9 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 3bc3159c83..b74f25a65d 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -211,7 +211,7 @@ chip northbridge/intel/gm45 device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index de5775558e..a1746bdee8 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -165,7 +165,7 @@ chip northbridge/intel/nehalem end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x2167 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index ae2a03ec09..a96026601f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -177,7 +177,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21db - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 41e13f6c75..01693c0430 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -132,7 +132,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end chip ec/lenovo/h8 @@ -179,7 +179,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21fa - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index cf319a36f3..da9bff7e41 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -204,7 +204,7 @@ chip northbridge/intel/i945 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 869e970cd4..1c60e6bf6b 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -139,7 +139,6 @@ chip northbridge/intel/i945 io 0x66 = 0x1604 end - register "config0" = "0xa6" register "config1" = "0x05" register "config2" = "0xa0" @@ -212,27 +211,26 @@ chip northbridge/intel/i945 subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 + subsystemid 0x17aa 0x200f + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" # vendor clockgen setup register "regs" = "{ 0x6d, 0xff, 0xff, 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - + device i2c 69 on end + end + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end end end end diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 7eaf78c9c9..35079255ad 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -47,7 +47,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB EHCI device pci 13.0 on end # USB OHCI device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS + device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address end @@ -57,7 +57,7 @@ chip northbridge/amd/agesa/family15tn/root_complex end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d + device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad register "multi_function_register_1" = "0x01" register "multi_function_register_2" = "0x0f" @@ -97,51 +97,51 @@ chip northbridge/amd/agesa/family15tn/root_complex io 0x60 = 0x225 # Fintek datasheet says 0x295. irq 0x70 = 0 end - device pnp 4e.05 on # KBC + device pnp 4e.05 on # KBC io 0x60 = 0x060 irq 0x70 = 1 # Keyboard IRQ irq 0x72 = 12 # Mouse IRQ end - device pnp 4e.06 on # GPIO + device pnp 4e.06 on # GPIO # ! GPIO config is disabled because the code in romstage.c # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status - - #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable - - #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data - - #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status - - #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status - - #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable - - #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end + #io 0x60 = 0xa00 + #irq 0xe0 = 0x04 # GPIO1 output + #irq 0xe1 = 0xff # GPIO1 output data + #irq 0xe3 = 0x04 # GPIO1 drive enable + #irq 0xe4 = 0x00 # GPIO1 PME enable + #irq 0xe5 = 0x00 # GPIO1 input detect select + #irq 0xe6 = 0x40 # GPIO1 event status + + #irq 0xd0 = 0x00 # GPIO2 output + #irq 0xd1 = 0xff # GPIO2 output data + #irq 0xd3 = 0x00 # GPIO2 drive enable + + #irq 0xc0 = 0x00 # GPIO3 output + #irq 0xc1 = 0xff # GPIO3 output data + + #irq 0xb0 = 0x04 # GPIO4 output + #irq 0xb1 = 0x04 # GPIO4 output data + #irq 0xb3 = 0x04 # GPIO4 drive enable + #irq 0xb4 = 0x00 # GPIO4 PME enable + #irq 0xb5 = 0x00 # GPIO4 input detect select + #irq 0xb6 = 0x00 # GPIO4 event status + + #irq 0xa0 = 0x00 # GPIO5 output + #irq 0xa1 = 0x1f # GPIO5 output data + #irq 0xa3 = 0x00 # GPIO5 drive enable + #irq 0xa4 = 0x00 # GPIO5 PME enable + #irq 0xa5 = 0xff # GPIO5 input detect select + #irq 0xa6 = 0xe0 # GPIO5 event status + + #irq 0x90 = 0x00 # GPIO6 output + #irq 0x91 = 0xff # GPIO6 output data + #irq 0x93 = 0x00 # GPIO6 drive enable + + #irq 0x80 = 0x00 # GPIO7 output + #irq 0x81 = 0xff # GPIO7 output data + #irq 0x83 = 0x00 # GPIO7 drive enable + end device pnp 4e.07 on end # WDT device pnp 4e.08 off end # CIR diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 51d5bf3425..c6dae6d451 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -13,153 +13,153 @@ ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9652 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1462 0x9652 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on # Link 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + # chip drivers/generic/generic # MAC EEPROM + # device i2c 51 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # HT 1.0 + device pci 18.0 on end # HT 2.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end end diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 20e865ab60..8cb8dd3b03 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,10 +69,10 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init. @@ -81,5 +81,4 @@ chip northbridge/amd/lx device lapic 0 on end end end - end diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index f8368ed7fa..e684a8f1a4 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -21,18 +21,18 @@ chip northbridge/amd/lx register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" - register "com2_enable" = "1" # Wired on Alix.2D13 only + register "com2_enable" = "1" # Wired on Alix.2D13 only register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired) register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired) - register "unwanted_vpci[2]" = "0" # End of list has a zero + register "unwanted_vpci[2]" = "0" # End of list has a zero device pci f.0 on end # ISA Bridge device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init. @@ -41,5 +41,4 @@ chip northbridge/amd/lx device lapic 0 on end end end - end diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 18dffcf2b5..08ba50607b 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -64,10 +64,10 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" register "pirqa_routing" = "PCH_IRQ11" @@ -211,12 +211,12 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end + chip ec/purism/librem + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 01445dcb8f..4ba6ccddba 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -64,10 +64,10 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" register "pirqa_routing" = "PCH_IRQ11" @@ -218,12 +218,12 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end + chip ec/purism/librem + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index 84845becb0..6a4d701988 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -37,7 +37,7 @@ Scope (\_TZ) // Method (_AC1, 0, Serialized) // { - // Return (0xf5c) + // Return (0xf5c) // } // Critical shutdown temperature diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 28f8f434c1..bb057f15c3 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -19,23 +19,23 @@ chip northbridge/intel/i945 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end register "pci_mmio_size" = "768" - device domain 0 on - subsystemid 0x4352 0x6886 inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x4352 0x6886 inherit + device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" register "pirqc_routing" = "0x0b" @@ -58,26 +58,26 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on chip southbridge/ti/pci7420 - register "smartcard_enabled" = "0x0" + register "smartcard_enabled" = "0x0" device pci 3.0 on end device pci 3.1 on end device pci 3.2 on end @@ -86,19 +86,19 @@ chip northbridge/intel/i945 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47n227 + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + io 0x60 = 0x3f8 + irq 0x70 = 4 end device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + io 0x60 = 0x2f8 + irq 0x70 = 3 end device pnp 2e.5 off # Keyboard+Mouse # io 0x60 = 0x60 @@ -106,7 +106,7 @@ chip northbridge/intel/i945 # irq 0x70 = 1 # irq 0x72 = 12 end - end + end chip superio/renesas/m3885x device pnp ff.1 on # dummy address end @@ -114,11 +114,11 @@ chip northbridge/intel/i945 chip ec/acpi end - end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index d5f744e98f..b51c86efe2 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -115,7 +115,7 @@ chip northbridge/intel/sandybridge chip superio/ite/it8783ef register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "ec.vin_mask" = "VIN_ALL" + register "ec.vin_mask" = "VIN_ALL" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" register "FAN1.smart.tmpin" = " 1" register "FAN1.smart.tmp_off" = "60" diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 9e52d07f56..ee88c31a97 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -1,152 +1,152 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2.0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 6956b45f7e..317d643d9a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -1,115 +1,115 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end - end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end + end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 485c7e0ef9..e49e16b94e 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -1,141 +1,141 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 4.0 on end - end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x10f1 0x2912 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 4.0 on end + end + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end end diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 14e3c537f7..bc03d21248 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -266,7 +266,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h index c3cd965c8b..211ee240ab 100644 --- a/src/northbridge/amd/agesa/family14/chip.h +++ b/src/northbridge/amd/agesa/family14/chip.h @@ -26,8 +26,8 @@ struct northbridge_amd_agesa_family14_config * * register "spdAddrLookup" = " * { // Use 8-bit SPD addresses here - * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) + * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 + * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) * }" * */ diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index be6f0ef062..5db6886e41 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -123,7 +123,7 @@ static void setup_default_resource_map(void) * [31: 8] Memory-Mapped I/O Limit Address i (39-16) * This field defines the upp adddress bits of a 40-bit * address that defines the end of a memory-mapped - * I/O region n + * I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -158,7 +158,7 @@ static void setup_default_resource_map(void) * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) * This field defines the upper address bits of a 40bit - * address that defines the start of memory-mapped + * address that defines the start of memory-mapped * I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h index 58673aaee3..7baba303dc 100644 --- a/src/northbridge/amd/amdht/h3gtopo.h +++ b/src/northbridge/amd/amdht/h3gtopo.h @@ -256,7 +256,7 @@ static u8 const amdHtTopologySevenTwistedLadder[] = { 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5 - 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 + 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 }; diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 58f43f1500..03d9bb3477 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -71,10 +71,10 @@ #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) #define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) -#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) +#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) -#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 8bee4344e7..4267e6d07c 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3752,10 +3752,11 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30]) - * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines - * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30]) + * a) Disable Compensation (F2[1, 0]9C_x08[30]) + * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in + * all the compensation engines + * c) Do frequency change + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c index 59618f6cc0..d826fed96d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -218,7 +218,7 @@ void ReadL18TestPattern(u32 addr_lo) // set fs and use fs prefix to access the mem __asm__ volatile ( "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line "movl %%fs:-64(%%esi), %%eax\n\t" //+1 "movl %%fs:(%%esi), %%eax\n\t" //+2 "movl %%fs:64(%%esi), %%eax\n\t" //+3 diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 71400071cf..9bb87bbb2a 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -461,7 +461,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, continue; } - BanksPresent = 1; /* flag for at least one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4); @@ -762,7 +762,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS test_buf += 2; } - bytelane = 0; /* bytelane counter */ + bytelane = 0; /* bytelane counter */ bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 9b22c84449..18774ebe7a 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -96,7 +96,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ + OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ nvbits = mctGet_NVbits(NV_DCBKScrub); diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index deb0f8a2e5..1e47ab4c39 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -36,11 +36,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. * Bottom40bIO = top of memory, right justified 8 bits - * (defines dram versus IO space type) + * (defines dram versus IO space type) * Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) + * (defines dram versus IO space type) * Cache32bTOP = sub 4GB top of WB cacheable memory, - * right justified 8 bits + * right justified 8 bits */ val = mctGet_NVbits(NV_BottomIO); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 60857f4052..a29f8eb42e 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -450,7 +450,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index da803ff627..7421c18a69 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2346,7 +2346,7 @@ void set_2t_configuration(struct MCTStatStruc *pMCTstat, enable_slow_access_mode = 1; } - reg = 0x94; /* DRAM Configuration High */ + reg = 0x94; /* DRAM Configuration High */ dword = Get_NB32_DCT(dev, dct, reg); if (enable_slow_access_mode) dword |= (0x1 << 20); /* Set 2T CMD mode */ @@ -2539,7 +2539,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat, uint32_t dword; dword = Get_NB32(pDCTstat->dev_dct, 0x118); - dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ + dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ dword |= (enable & 0x1) << 18; Set_NB32(pDCTstat->dev_dct, 0x118, dword); } @@ -7908,10 +7908,11 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30]) - * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines - * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30]) + * a) Disable Compensation (F2[1, 0]9C_x08[30]) + * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in + * all the compensation engines + * c) Do frequency change + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index d4b37921c4..a02f49b5c6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -134,7 +134,7 @@ #define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/ #define RDqsEn 12 /* func 2, offset 94h, bit 12*/ #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ -#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ +#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index f751733f73..9b7481717d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1102,7 +1102,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); +// dword |= (0x55555); dword |= (0x44443); /* Use AGESA seed */ Set_NB32_DCT(dev, dct, 0x270, dword); @@ -1199,7 +1199,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); +// dword |= (0x55555); dword |= (0x44443); /* Use AGESA seed */ Set_NB32_DCT(dev, dct, 0x270, dword); @@ -1633,7 +1633,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; - uint16_t ren_step = 0x40; + uint16_t ren_step = 0x40; uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 9aad96cfbc..31c23b9445 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -115,12 +115,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ + OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ if (!is_fam15h()) { nvbits = mctGet_NVbits(NV_DCBKScrub); - /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ + /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ OF_ScrubCTL |= (u32) nvbits << 16; nvbits = mctGet_NVbits(NV_L2BKScrub); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 8a1f7362a8..2bf85622e6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -40,11 +40,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. * Bottom40bIO = top of memory, right justified 8 bits - * (defines dram versus IO space type) + * (defines dram versus IO space type) * Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) + * (defines dram versus IO space type) * Cache32bTOP = sub 4GB top of WB cacheable memory, - * right justified 8 bits + * right justified 8 bits */ val = mctGet_NVbits(NV_BottomIO); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 984f604135..7c3781fb40 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1002,7 +1002,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1505,7 +1505,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1725,7 +1725,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index a351e8dfb5..84e26eadea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -707,7 +707,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste * For now, skip restoration... */ // for (i = 0; i < 8; i++) - // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); + // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); wrmsr_uint64_t(0x000002ff, data->msr000002ff); wrmsr_uint64_t(0xc0010010, data->msrc0010010); wrmsr_uint64_t(0xc001001a, data->msrc001001a); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index b8a67ee2f8..6c2efb320c 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -594,7 +594,7 @@ static void rom_shadow_settings(void) * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 3be0248571..ab5c70f09f 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -419,8 +419,8 @@ static void set_latencies(void) /* tRC = tRP + tRAS */ dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + - ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) - << CF8F_LOWER_ACT2ACTREF_SHIFT; + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) + << CF8F_LOWER_ACT2ACTREF_SHIFT; msr = rdmsr(MC_CF8F_DATA); msr.lo &= 0xF00000FF; diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 5ceeacceaf..b80d8a8a52 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -26,7 +26,7 @@ #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ #define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define PAM_0 0x59 +#define PAM_0 0x59 #define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ #define DRB_ROW_1 0x61 diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 54b1ede72a..54508fe956 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -199,7 +199,7 @@ static void callout_ap_entry(void *unused) { AGESA_STATUS Status = AGESA_UNSUPPORTED; - printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p \n", + printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p\n", __func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr); /* Check if this AP should run the function */ diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 2528294a7d..84a55430c9 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -104,8 +104,8 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; #if DUMP_FCH_SETTING int i; diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 816988b53e..6f0826fee4 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -178,7 +178,7 @@ Method(_INI, 0) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ @@ -298,9 +298,9 @@ Scope(\){ PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ebc6ba1f8d..29a1336f13 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -28,7 +28,7 @@ #include <arch/acpi.h> #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platform Specific Definitions */ +#include "SBPLATFORM.h" /* Platform Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ @@ -352,13 +352,13 @@ static void sb800_enable(struct device *dev) switch (dev->path.pci.devfn) { case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } break; @@ -387,11 +387,11 @@ static void sb800_enable(struct device *dev) case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { - sb_config->AzaliaController = AZALIA_AUTO; + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; } } else { - sb_config->AzaliaController = AZALIA_DISABLE; + sb_config->AzaliaController = AZALIA_DISABLE; } break; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index e792fe3c61..158e3f4a1e 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -25,8 +25,8 @@ #include <device/pci_ehci.h> #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ -#include "SbPlatform.h" /* Platform Specific Definitions */ -#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ +#include "SbPlatform.h" /* Platform Specific Definitions */ +#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ #ifndef _RAMSTAGE_ #define _RAMSTAGE_ @@ -353,13 +353,13 @@ static void sb900_enable(struct device *dev) case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; + sb_config->SATAMODE.SataMode.SataController = ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; + sb_config->SATAMODE.SataMode.SataController = DISABLED; } //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY @@ -380,19 +380,19 @@ static void sb900_enable(struct device *dev) if (dev->enabled) { sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; } //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { - sb_config->AzaliaController = AZALIA_AUTO; + if (sb_config->AzaliaController == AZALIA_DISABLE) { + sb_config->AzaliaController = AZALIA_AUTO; } printk(BIOS_DEBUG, "hda enabled\n"); } else { - sb_config->AzaliaController = AZALIA_DISABLE; + sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } //- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio @@ -446,7 +446,7 @@ static void sb900_enable(struct device *dev) /* Special setting ABCFG registers before PCI emulation. */ //- abSpecialSetBeforePciEnum(sb_config); -//- usbDesertPll(sb_config); +//- usbDesertPll(sb_config); //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; //AmdSbDispatcher(sb_config); } diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 5f20c12843..956994d623 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -514,7 +514,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /**************************************************************************** * - * ChipsetInit + * ChipsetInit * * Called from northbridge init (Pre-VSA). * diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 72dbd5c216..4083f4f4eb 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -413,7 +413,7 @@ /* FLASH device macros */ #define FLASH_TYPE_NONE 0 /* No flash device installed */ -#define FLASH_TYPE_NAND 1 /* NAND device */ +#define FLASH_TYPE_NAND 1 /* NAND device */ #define FLASH_TYPE_NOR 2 /* NOR device */ #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 679f233f02..1b5326b88e 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -46,7 +46,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SD 0x17 /* SD */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index d95385be1e..b5a86dc959 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -163,7 +163,7 @@ static void enable_wideio(uint8_t port, uint16_t size) tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp |= alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); - } else { /* 512 */ + } else { /* 512 */ tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp &= ~alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 091464f14d..922c608a67 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -121,7 +121,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 -#define SPI_CNTRL0 0x00 +#define SPI_CNTRL0 0x00 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) /* Nominal is 16.7MHz on older devices, 33MHz on newer */ #define SPI_READ_MODE_NOM 0x00000000 @@ -137,7 +137,7 @@ #define SPI_CNTRL1 0x0c /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8 @@ -153,10 +153,10 @@ #define SPI_SPEED_800K (BIT(2) | BIT(0)) #define SPI_NORM_SPEED_NEW_SH 12 #define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_ALT_SPEED_NEW_SH 4 #define SPI_TPM_SPEED_NEW_SH 0 -#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) static inline int hudson_sata_enable(void) diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 7bc9435b5b..ab75e5f57f 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -24,7 +24,7 @@ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBMISC_INDEX 0x60 -#define NBMC_INDEX 0xE8 +#define NBMC_INDEX 0xE8 static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index cfcddb29f3..30345bef11 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -186,7 +186,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) printk(BIOS_DEBUG, "Dev ID %x\n", Value); if ((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB - u32 MMIOStart = 0xffffffff; + u32 MMIOStart = 0xffffffff; u32 MMIOLimit = 0; for (Reg = 0x10; Reg < 0x20; Reg+=4) { u32 BaseA, LimitA; @@ -449,7 +449,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulMinSidePortClock = 333*100; #endif - vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default + vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default // find the DDR memory frequency if (is_family10h()) { @@ -1109,8 +1109,8 @@ static void dual_port_configuration(struct device *nb_dev, struct device *dev) /* For single port GFX configuration Only * width: -* 000 = x16 -* 001 = x1 +* 000 = x16 +* 001 = x1 * 010 = x2 * 011 = x4 * 100 = x8 diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index ef40ffd060..f4f33efab7 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -93,7 +93,7 @@ void static rs780_config_misc_clk(struct device *nb_dev) byte |= 1 << 0; pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); - /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ + /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ #endif diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index ce46d96760..e96608eba9 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -22,10 +22,10 @@ #include "chip.h" #include "rev.h" -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 #define EXT_CONF_BASE_ADDRESS 0xE0000000 #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6211ddeec2..64c6db3072 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -225,7 +225,7 @@ static void sm_init(struct device *dev) pci_write_config8(dev, 0xE1, byte); /* 2.5 Enabling Non-Posted Memory Write */ - axindxc_reg(0x10, 1 << 9, 1 << 9); + axindxc_reg(0x10, 1 << 9, 1 << 9); /* 2.11 IO Trap Settings */ abcfg_reg(0x10090, 1 << 16, 1 << 16); diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 12b9dd673a..bf790565ee 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -215,14 +215,14 @@ static const struct pci_driver usb_1_driver __pci_driver = { /* the pci id of usb ctrl 0 and 1 are the same. */ /* * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0, * }; * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1, * }; */ @@ -248,8 +248,8 @@ static const struct pci_driver usb_5_driver __pci_driver = { }; /* * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2, + * .ops = &usb_ops2, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2, * }; */ diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index 2318a8ff8f..715095f443 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -166,14 +166,14 @@ static const struct pci_driver usb_1_driver __pci_driver = { /* the pci id of usb ctrl 0 and 1 are the same. */ /* * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0, * }; * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1, * }; */ @@ -199,8 +199,8 @@ static const struct pci_driver usb_5_driver __pci_driver = { }; /* * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2, + * .ops = &usb_ops2, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2, * }; */ diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index e44d1e89c0..859e15dd62 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -19,12 +19,12 @@ #include <arch/io.h> -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 -#define L2CFG_INDEX 0xF0 -#define L1CFG_INDEX 0xF8 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 +#define L2CFG_INDEX 0xF0 +#define L1CFG_INDEX 0xF8 #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9e2bd9233e..8986e676dc 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -454,14 +454,14 @@ static void EnableLclkGating(struct device *dev) reg = 0xE8; port = dev->path.pci.devfn >> 3; switch (port) { - //PCIE_CORE_INDEX_GPP1 + //PCIE_CORE_INDEX_GPP1 case 2: case 3: reg = 0x94; mask = 1 << 16; break; - //PCIE_CORE_INDEX_GPP2 + //PCIE_CORE_INDEX_GPP2 case 11: case 12: value = 1 << 28; @@ -479,7 +479,7 @@ static void EnableLclkGating(struct device *dev) value = 1 << 25; break; - //PCIE_CORE_INDEX_SB; + //PCIE_CORE_INDEX_SB; case 8: reg = 0x94; mask = 1 << 24; diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1962ea3277..fae26899ec 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -427,7 +427,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword |= (0x1 << 0); l2cfg_ind_write_index(nb_dev, 0x44, dword); -// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { +// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { dword = l2cfg_ind_read_index(nb_dev, 0x7); dword |= (0x1 << 1); l2cfg_ind_write_index(nb_dev, 0x7, dword); @@ -479,7 +479,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword = l2cfg_ind_read_index(nb_dev, 0x6); dword |= (0x1 << 8); l2cfg_ind_write_index(nb_dev, 0x6, dword); -// } +// } l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index b10c23fcd1..8619cbd32a 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -89,7 +89,7 @@ static void bcm5785_lpc_enable_childrens_resources(struct device *dev) case 0x64: reg |= (1<<29); break; case 0x3f8: // COM1 - reg |= (1<<6); break; + reg |= (1<<6); break; case 0x2f8: // COM2 reg |= (1<<7); break; case 0x378: // Parallel 1 diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 9f5033d759..a068bc039c 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -202,7 +202,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index f95a0b46a0..b0f2a6e90b 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -292,7 +292,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 wwan3gpresent : 1; @@ -350,7 +350,7 @@ typedef struct { typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e2ff851e42..622153cc1e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -188,7 +188,7 @@ void southbridge_smi_monitor(void) data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index d591bccf00..ea48d9e050 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -46,11 +46,11 @@ void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number) /* Device (SLOT) { - Name (_ADR, 0x00) - Method (_RMV, 0, NotSerialized) - { - Return (0x01) - } + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } } */ diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 99608dc10f..de4ff91cfd 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -54,7 +54,7 @@ #define SMBHSTSTS_HOST_BUSY (1 << 0) #define SMBUS_TIMEOUT (10 * 1000 * 100) -#define SMBUS_BLOCK_MAXLEN 32 +#define SMBUS_BLOCK_MAXLEN 32 static void smbus_delay(void) { diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl index 114aea6021..510749175b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl @@ -202,7 +202,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h index f95a0b46a0..b0f2a6e90b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ b/src/southbridge/intel/fsp_bd82x6x/me.h @@ -292,7 +292,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 wwan3gpresent : 1; @@ -350,7 +350,7 @@ typedef struct { typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 14637e62b3..22489040ae 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -324,7 +324,7 @@ void southbridge_clear_smi_status(void) reset_pm1_status(); /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 90ed943cba..c868ec6cf8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -659,7 +659,7 @@ static void southbridge_smi_monitor(void) data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl index f2015d3342..7036f33caa 100644 --- a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl +++ b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl @@ -202,7 +202,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h index f95a0b46a0..b0f2a6e90b 100644 --- a/src/southbridge/intel/fsp_i89xx/me.h +++ b/src/southbridge/intel/fsp_i89xx/me.h @@ -292,7 +292,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 wwan3gpresent : 1; @@ -350,7 +350,7 @@ typedef struct { typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 3658a82d4c..0ef7ba8ffb 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -659,7 +659,7 @@ static void southbridge_smi_monitor(void) data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 696a81ae65..b55bd92dd1 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -208,7 +208,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 3a08daad3f..b2b4662f60 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -542,7 +542,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 8a9aff4a48..cf158df729 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -129,7 +129,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 143ecb1f2d..52b263f3eb 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -132,7 +132,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index da8b789baa..985e8b657a 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -132,7 +132,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 35e79c6064..f4382d74f1 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -402,7 +402,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 84ae47d3ef..1fe40b6e6f 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -16,9 +16,9 @@ #define ABAR 0x40 /* for pci bridge 1460 */ -#define MTT 0x042 -#define HCCR 0x0f0 -#define ACNF 0x0e0 +#define MTT 0x042 +#define HCCR 0x0f0 +#define ACNF 0x0e0 #define STRP 0x44 // Strap status register #define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN) diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index d62b22ad5e..6423d8d29d 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -191,7 +191,7 @@ struct mei_header { #define MKHI_MDES_ENABLE 0x09 #define MKHI_GET_FW_VERSION 0x02 -#define MKHI_SET_UMA 0x08 +#define MKHI_SET_UMA 0x08 #define MKHI_END_OF_POST 0x0c #define MKHI_FEATURE_OVERRIDE 0x14 @@ -293,7 +293,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 wwan3gpresent : 1; @@ -351,7 +351,7 @@ typedef struct { typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index fbbd26d66f..eaa2690765 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -45,7 +45,7 @@ Scope(\) Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index a1987eb55e..cef2e55a24 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -374,7 +374,7 @@ void intel_me8_finalize_smm(void); typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __packed mbp_header; typedef struct { @@ -459,7 +459,7 @@ typedef struct { typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; - u16 s3authentication : 1; + u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 70f2834cd0..ae996e866e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -392,8 +392,8 @@ void pch_enable_lpc(void); #define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ #define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 5cdd99d431..87848c23c7 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -450,7 +450,7 @@ static void southbridge_smi_monitor(void) data = RCBA32(0x1e18); data &= mask; // if (smi1) - // southbridge_smi_command(data); + // southbridge_smi_command(data); // return; } // Fall through to debug diff --git a/src/southbridge/via/common/early_smbus_print_error.c b/src/southbridge/via/common/early_smbus_print_error.c index 842c5d646d..1aafcf31d3 100644 --- a/src/southbridge/via/common/early_smbus_print_error.c +++ b/src/southbridge/via/common/early_smbus_print_error.c @@ -25,7 +25,7 @@ * a transaction is processed. * @param loops The number of times a transaction was attempted. * @return 0 if no error occurred - * 1 if an error was detected + * 1 if an error was detected */ int smbus_print_error(u32 smbus_dev, u8 host_status, int loops) { diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 21174b03c9..67a2c56994 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -88,16 +88,16 @@ up in SPD. Under Linux you can see present SPD addresses with following commands phcoder@sid:~/coreboot/util/autoport$ sudo modprobe i2c-dev phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect -l - i2c-0 i2c i915 gmbus ssc I2C adapter - i2c-1 i2c i915 gmbus vga I2C adapter - i2c-2 i2c i915 gmbus panel I2C adapter - i2c-3 i2c i915 gmbus dpc I2C adapter - i2c-4 i2c i915 gmbus dpb I2C adapter - i2c-5 i2c i915 gmbus dpd I2C adapter - i2c-6 i2c DPDDC-B I2C adapter - i2c-7 i2c DPDDC-C I2C adapter - i2c-8 i2c DPDDC-D I2C adapter - i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter + i2c-0 i2c i915 gmbus ssc I2C adapter + i2c-1 i2c i915 gmbus vga I2C adapter + i2c-2 i2c i915 gmbus panel I2C adapter + i2c-3 i2c i915 gmbus dpc I2C adapter + i2c-4 i2c i915 gmbus dpb I2C adapter + i2c-5 i2c i915 gmbus dpd I2C adapter + i2c-6 i2c DPDDC-B I2C adapter + i2c-7 i2c DPDDC-C I2C adapter + i2c-8 i2c DPDDC-D I2C adapter + i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect 9 WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-9. diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index addc61f186..cd8a091989 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1191,7 +1191,7 @@ export PATH=$DESTDIR$TARGETDIR/bin:$PATH # Download, unpack, patch and build all packages -printf "Downloading and verifing tarballs ... \n" +printf "Downloading and verifing tarballs ...\n" mkdir -p tarballs for P in $PACKAGES; do download "$P" || exit "$?" @@ -1199,21 +1199,21 @@ for P in $PACKAGES; do done printf "Downloaded tarballs ... ${green}ok${NC}\n" -printf "Unpacking and patching ... \n" +printf "Unpacking and patching ...\n" for P in $PACKAGES; do unpack_and_patch $P || exit 1 done printf "Unpacked and patched ... ${green}ok${NC}\n" if [ -n "$BOOTSTRAPONLY" ]; then - printf "Building bootstrap compiler only ... \n" + printf "Building bootstrap compiler only ...\n" for pkg in GMP MPFR MPC GCC; do build_for_host $pkg done exit 0 fi -printf "Building packages ... \n" +printf "Building packages ...\n" for package in $PACKAGES; do build $package done diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index ff69d7e7a5..dfd5cbb92b 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -76,7 +76,7 @@ struct me_hfs { uint32_t boot_options_present: 1; uint32_t ack_data: 3; uint32_t bios_msg_ack: 4; -} __attribute__ ((packed)); +} __attribute__((packed)); #define PCI_ME_UMA 0x44 @@ -86,7 +86,7 @@ struct me_uma { uint32_t valid: 1; uint32_t reserved_0: 14; uint32_t set_to_one: 1; -} __attribute__ ((packed)); +} __attribute__((packed)); #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -99,7 +99,7 @@ struct me_did { uint32_t reserved: 8; uint32_t status: 4; uint32_t init_done: 4; -} __attribute__ ((packed)); +} __attribute__((packed)); #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -125,7 +125,7 @@ struct me_gmes { uint32_t current_state: 8; uint32_t current_pmevent: 4; uint32_t progress_code: 4; -} __attribute__ ((packed)); +} __attribute__((packed)); #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -137,14 +137,14 @@ struct me_heres { uint32_t reserved: 26; uint32_t extend_feature_present: 1; uint32_t extend_reg_valid: 1; -} __attribute__ ((packed)); +} __attribute__((packed)); struct me_thermal_reporting { uint32_t polling_timeout: 8; uint32_t smbus_ec_msglen: 8; uint32_t smbus_ec_msgpec: 8; uint32_t dimmnumber: 8; -} __attribute__ ((packed)); +} __attribute__((packed)); /* * Management Engine MEI registers @@ -165,7 +165,7 @@ struct mei_csr { uint32_t buffer_read_ptr: 8; uint32_t buffer_write_ptr: 8; uint32_t buffer_depth: 8; -} __attribute__ ((packed)); +} __attribute__((packed)); #define MEI_ADDRESS_HBM 0x00 #define MEI_ADDRESS_CORE_WD 0x01 @@ -187,7 +187,7 @@ struct mei_header { uint32_t length: 9; uint32_t reserved: 6; uint32_t is_complete: 1; -} __attribute__ ((packed)); +} __attribute__((packed)); #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_PM 0x01 @@ -231,7 +231,7 @@ struct mkhi_header { uint32_t is_response: 1; uint32_t reserved: 8; uint32_t result: 8; -} __attribute__ ((packed)); +} __attribute__((packed)); struct me_fw_version { uint16_t code_minor; @@ -246,7 +246,7 @@ struct me_fw_version { uint16_t fitcmajor; uint16_t fitcbuildno; uint16_t fitchotfix; -} __attribute__ ((packed)); +} __attribute__((packed)); #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -261,7 +261,7 @@ struct me_fw_version { struct me_global_reset { uint8_t request_origin; uint8_t reset_type; -} __attribute__ ((packed)); +} __attribute__((packed)); typedef enum { ME_NORMAL_BIOS_PATH, @@ -277,7 +277,7 @@ typedef struct { uint32_t minor_version : 16; uint32_t hotfix_version : 16; uint32_t build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __attribute__((packed)) mbp_fw_version_name; typedef struct { uint8_t num_icc_profiles; @@ -285,7 +285,7 @@ typedef struct { uint8_t icc_profile_index; uint8_t reserved; uint32_t register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __attribute__((packed)) mbp_icc_profile; typedef struct { uint32_t full_net : 1; @@ -308,7 +308,7 @@ typedef struct { uint32_t reserved_4 : 1; uint32_t wlan : 1; uint32_t reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __attribute__((packed)) mefwcaps_sku; typedef struct { uint16_t lock_state : 1; @@ -319,13 +319,13 @@ typedef struct { uint16_t wwan3gpresent : 1; uint16_t wwan3goob : 1; uint16_t reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __attribute__((packed)) tdt_state_flag; typedef struct { uint8_t state; uint8_t last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __attribute__((packed)) tdt_state_info; typedef struct { uint32_t platform_target_usage_type : 4; @@ -335,7 +335,7 @@ typedef struct { uint32_t intel_me_fw_image_type : 4; uint32_t platform_brand : 4; uint32_t reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __attribute__((packed)) platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -346,7 +346,7 @@ typedef struct { uint16_t device_id; uint16_t fuse_test_flags; uint32_t umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __attribute__((packed)) mbp_rom_bist_data; typedef struct { uint32_t key[8]; @@ -372,28 +372,28 @@ typedef struct { uint32_t mbp_size : 8; uint32_t num_entries : 8; uint32_t rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __attribute__((packed)) mbp_header; typedef struct { uint32_t app_id : 8; uint32_t item_id : 8; uint32_t length : 8; uint32_t rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __attribute__((packed)) mbp_item_header; struct me_fwcaps { uint32_t id; uint8_t length; mefwcaps_sku caps_sku; uint8_t reserved[3]; -} __attribute__ ((packed)); +} __attribute__((packed)); struct me_debug_mem { uint32_t debug_phys; uint32_t debug_size; uint32_t me_phys; uint32_t me_size; -} __attribute__ ((packed)); +} __attribute__((packed)); void intel_me_status(uint32_t hfs, uint32_t gmes); void mkhi_thermal(void); diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 9a7d1a2ff6..ebea26ff79 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -9199,7 +9199,7 @@ static void decompose_compound_types(struct compile_state *state) } #if DEBUG_DECOMPOSE_HIRES - fprintf(fp, "decompose next: %p \n", next); + fprintf(fp, "decompose next: %p\n", next); fflush(fp); fprintf(fp, "next->op: %d %s\n", next->op, tops(next->op)); @@ -14284,7 +14284,7 @@ static void compute_closure_variables(struct compile_state *state, #if DEBUG_EXPLICIT_CLOSURES /* Print out the variables to be enclosed */ loc(state->dbgout, state, fcall); - fprintf(state->dbgout, "Alive: \n"); + fprintf(state->dbgout, "Alive:\n"); for(set = *enclose; set; set = set->next) { display_triple(state->dbgout, set->member); } @@ -25048,7 +25048,7 @@ static void usage(void) fprintf(fp, "\nUsage: romcc [options] <source>.c\n" "Compile a C source file generating a binary that does not implicilty use RAM\n" - "Options: \n" + "Options:\n" "-o <output file name>\n" "-f<option> Specify a generic compiler option\n" "-m<option> Specify a arch dependent option\n" diff --git a/util/vgabios/device.c b/util/vgabios/device.c index 3526e24716..ecd2481a56 100644 --- a/util/vgabios/device.c +++ b/util/vgabios/device.c @@ -80,7 +80,8 @@ biosemu_dev_get_addr_info(void) taa_index++; /* legacy ranges if its a VGA card... */ if ((bios_device.dev->class & 0xFF0000) == 0x030000) { - DEBUG_PRINTF("%s: VGA device found, adding legacy resources... \n", __func__); + DEBUG_PRINTF("%s: VGA device found, adding legacy resources..." + "\n", __func__); /* I/O 0x3B0-0x3BB */ translate_address_array[taa_index].info = IORESOURCE_FIXED | IORESOURCE_IO; translate_address_array[taa_index].bus = bus; @@ -116,7 +117,7 @@ biosemu_dev_get_addr_info(void) taa_last_entry = taa_index - 1; #if CONFIG_X86EMU_DEBUG //dump translate_address_array - printf("translate_address_array: \n"); + printf("translate_address_array:\n"); translate_address_t ta; int i; for (i = 0; i <= taa_last_entry; i++) { @@ -201,7 +202,7 @@ biosemu_dev_get_addr_info(void) taa_last_entry = taa_index - 1; #if CONFIG_X86EMU_DEBUG //dump translate_address_array - printf("translate_address_array: \n"); + printf("translate_address_array:\n"); translate_address_t ta; for (i = 0; i <= taa_last_entry; i++) { ta = translate_address_array[i]; diff --git a/util/vgabios/testbios.c b/util/vgabios/testbios.c index aedeb1d217..de537b8fcd 100644 --- a/util/vgabios/testbios.c +++ b/util/vgabios/testbios.c @@ -116,8 +116,8 @@ int printk(int msg_level, const char *fmt, ...) static void usage(char *name) { printf - ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ... \n", - name); + ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] " + "<filename> ...\n", name); } /* main entry into YABEL biosemu, arguments are: @@ -218,7 +218,7 @@ int main(int argc, char **argv) debugflag = strtol(optarg, 0, 0); break; default: - printf("Unknown option \n"); + printf("Unknown option\n"); usage(argv[0]); return 1; } |