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authorArthur Heymans <arthur@aheymans.xyz>2017-09-21 18:57:19 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-09-23 22:29:09 +0000
commitb47444533bf9593b87e5bfc938361817e56300f5 (patch)
tree7e7c8cba4c80040bb07e1433698c936bf228d1e3
parentb29078e4015bbc3e8cf00ba64f0799c087546563 (diff)
downloadcoreboot-b47444533bf9593b87e5bfc938361817e56300f5.tar.xz
mb/intel/dg43gt: Set SuperIO gpio correctly
Set SuperIO GPIO like vendor firmware. Change-Id: I46a48776382eb0d9be9727691c68912991e14dfe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/mainboard/intel/dg43gt/devicetree.cb14
1 files changed, 9 insertions, 5 deletions
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
index 79a8eb7309..6d87794fe3 100644
--- a/src/mainboard/intel/dg43gt/devicetree.cb
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -83,12 +83,16 @@ chip northbridge/intel/x4x # Northbridge
irq 0xf0 = 0x85
end
device pnp 2e.6 off end # SPI
- device pnp 2e.7 on # GPIO 6
- irq 0x30 = 0x06
- end
+ device pnp 2e.7 on end # GPIO 6
device pnp 2e.8 off end # WDTO# PLED
- device pnp 2e.9 on # GPIO 2,3,4,5
- irq 0x30 = 0x0a
+ device pnp 2e.9 off end # GPIO 2
+ device pnp 2e.109 on # GPIO 3
+ irq 0xf0 = 0xfc
+ end
+ device pnp 2e.209 off end # GPIO 4
+ device pnp 2e.309 on # GPIO 5
+ irq 0xe0 = 0xde
+ irq 0xe1 = 0x01
end
device pnp 2e.a on # ACPI
irq 0xe4 = 0x30 # power dram during S3