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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-02-25 23:20:14 -0600
committerMartin Roth <martinroth@google.com>2016-02-26 20:05:16 +0100
commitba894be382c1a0365c435d5be2b54422731d66c8 (patch)
tree73678d140d2ed454976028c451c8ed4c3b0ca5ff
parentd912f1d4f973f415a431932b71e9cee0b1c82549 (diff)
downloadcoreboot-ba894be382c1a0365c435d5be2b54422731d66c8.tar.xz
During DRAM initialization on certain ASpeed devices, an incorrect
bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13807 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/drivers/aspeed/common/ast_main.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
index 071e49caf2..264ef9d42d 100644
--- a/src/drivers/aspeed/common/ast_main.c
+++ b/src/drivers/aspeed/common/ast_main.c
@@ -232,7 +232,7 @@ static int ast_get_dram_info(struct drm_device *dev)
data = ast_read32(ast, 0x10004);
- if (data & 0x400)
+ if (data & 0x40)
ast->dram_bus_width = 16;
else
ast->dram_bus_width = 32;