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authorIsaac Christensen <isaac.christensen@se-eng.com>2014-09-11 11:02:29 -0600
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-12 21:59:23 +0200
commitbca446d47162233232209b04d1c8f78a01fcd41f (patch)
tree75211ea735fcd23f0e6ee4f7875f3482578dae73
parent3f0f300bcf16c91c3b7763051be648caf778ec69 (diff)
downloadcoreboot-bca446d47162233232209b04d1c8f78a01fcd41f.tar.xz
panther: update chromeos.c
The google mainboards were updated to unconditionally include chromeos.c except for panther. Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/panther/Makefile.inc4
-rw-r--r--src/mainboard/google/panther/chromeos.c25
2 files changed, 8 insertions, 21 deletions
diff --git a/src/mainboard/google/panther/Makefile.inc b/src/mainboard/google/panther/Makefile.inc
index 7533fcfa2d..2932f4d4a5 100644
--- a/src/mainboard/google/panther/Makefile.inc
+++ b/src/mainboard/google/panther/Makefile.inc
@@ -17,8 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += chromeos.c
+ramstage-y += chromeos.c
ramstage-y += lan.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c
index 62165daed2..b35bf56d27 100644
--- a/src/mainboard/google/panther/chromeos.c
+++ b/src/mainboard/google/panther/chromeos.c
@@ -19,7 +19,7 @@
#include <string.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
+#include <bootmode.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -32,23 +32,10 @@
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
-#define GPIO_COUNT 6
-#define ACTIVE_LOW 0
-#define ACTIVE_HIGH 1
-
#ifndef __PRE_RAM__
-static void fill_lb_gpio(struct lb_gpio *gpio, int num,
- int polarity, const char *name, int force)
-{
- memset(gpio, 0, sizeof(*gpio));
- gpio->port = num;
- gpio->polarity = polarity;
- if (force >= 0)
- gpio->value = force;
- else if (num >= 0)
- gpio->value = get_gpio(num);
- strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
-}
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT 6
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -65,7 +52,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
get_developer_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
}
#endif
@@ -97,7 +84,7 @@ int get_recovery_mode_switch(void)
}
#ifdef __PRE_RAM__
-void save_chromeos_gpios(void)
+void init_bootmode_straps(void)
{
u32 flags = 0;