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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-05 15:56:18 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-14 15:16:19 +0000
commitccb53e181726ddd90ec6d5a2b6d6b62ab8bd6a70 (patch)
tree93cab9d95f1c61d8bc2b77150f2669fe88089b5d
parent9c790a2fdc1fdf98cbc8fe92a6662c475ce36bed (diff)
downloadcoreboot-ccb53e181726ddd90ec6d5a2b6d6b62ab8bd6a70.tar.xz
binaryPI: Fix cache coherency use for AP CPUs
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc7
-rw-r--r--src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc7
-rw-r--r--src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc7
-rw-r--r--src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc7
4 files changed, 28 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index f444852e54..51c6b52248 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -1438,6 +1438,13 @@ SetupStack:
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 0fbcf77eea..b9cc39fac5 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -1179,6 +1179,13 @@ w64k_here:
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 2399bec91b..46946327ce 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -1158,6 +1158,13 @@ w64k_here:
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 7e12db1d06..6c4ad596e1 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -1153,6 +1153,13 @@ SetupStack:
0:
_WRMSR #
+ # All cores must see BSP stack region that is also used to
+ # communicate global variables before DRAM is up.
+ mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
+ _RDMSR
+ or $0x1e000000, %eax
+ _WRMSR #
+
# Enable MTRR defaults as UC type
mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
_RDMSR # Read-modify-write the MSR