diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
920 files changed, 2285 insertions, 2285 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 80023c4418..14f5f7ade9 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -37,7 +37,7 @@ #include <arch/cache.h> -#if IS_ENABLED(CONFIG_ARM_LPAE) +#if CONFIG(ARM_LPAE) /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ #define ATTR_BLOCK (\ @@ -170,7 +170,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry) /* Initialize the new subtable with entries of the same attributes * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */ pte_t attr = *pgd_entry & ~(BLOCK_MASK); - if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4))) + if (!CONFIG(ARM_LPAE) && (attr & (1 << 4))) attr = ((attr & ~(1 << 4)) | (1 << 0)); if (attr & ATTR_BLOCK) attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE; @@ -208,7 +208,7 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy) /* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */ pte_t attr = attrs[policy].value; - if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4))) + if (!CONFIG(ARM_LPAE) && (attr & (1 << 4))) attr = ((attr & ~(1 << 4)) | (1 << 0)); /* Mask away high address bits that are handled by upper level table. */ diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index f7837b68c8..4ba2bf8cf2 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -18,16 +18,16 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) +#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M) #define TTB(addr, size) \ REGION(ttb, addr, size, 16K) \ - _ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \ + _ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \ "TTB must be 16K (+ 32 for LPAE)!"); #define TTB_SUBTABLES(addr, size) \ - REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \ - _ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \ + REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \ + _ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \ "TTB subtable region must be evenly divisible by table size!"); /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 9a8021761e..b2b6a33333 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -134,7 +134,7 @@ static inline void write_mair0(uint32_t val) /* write translation table base register 0 (TTBR0) */ static inline void write_ttbr0(uint32_t val) { - if (IS_ENABLED(CONFIG_ARM_LPAE)) + if (CONFIG(ARM_LPAE)) asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : : [val] "r" (val), [zero] "r" (0)); else diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 7f8e2a03f0..682715f8c1 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -32,7 +32,7 @@ void bootmem_arch_add_ranges(void) bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables), BM_MEM_RAMSTAGE); - if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER)) + if (!CONFIG(COMMON_CBFS_SPI_WRAPPER)) return; bootmem_add_range((uintptr_t)_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE); diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 3f1aa2a265..7cf173b5bb 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -56,7 +56,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); - if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) { + if (CONFIG(ARM64_USE_SECURE_OS)) { struct prog bl32 = PROG_INIT(PROG_BL32, CONFIG_CBFS_PREFIX"/secure_os"); diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index e32c79a85a..58a35238f6 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -220,7 +220,7 @@ void exception_init(void) printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n"); /* Only spend time testing on debug builds that are trying to detect more errors. */ - if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) { + if (CONFIG(FATAL_ASSERTS)) { printk(BIOS_DEBUG, "ARM64: Testing exception\n"); test_exception(); printk(BIOS_DEBUG, "ARM64: Done test exception\n"); diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index c2119f3890..fefc0d305e 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -30,7 +30,7 @@ static void run_payload(struct prog *prog) arg = prog_entry_arg(prog); u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L); - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr); else transition_to_el2(doit, arg, payload_spsr); diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h index 397ac2aa67..3c3feb68d7 100644 --- a/src/arch/arm64/include/armv8/arch/barrier.h +++ b/src/arch/arm64/include/armv8/arch/barrier.h @@ -30,7 +30,7 @@ #define rmb() asm volatile("dsb ld" : : : "memory") #define wmb() asm volatile("dsb st" : : : "memory") -#if IS_ENABLED(CONFIG_SMP) +#if CONFIG(SMP) #define barrier() __asm__ __volatile__("": : :"memory") #endif diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index b0010c4b9e..492eadd764 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -30,12 +30,12 @@ void bootmem_arch_add_ranges(void) { bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE); - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) && + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE) && REGION_SIZE(bl31) > 0) bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31), BM_MEM_BL31); - if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER)) + if (!CONFIG(COMMON_CBFS_SPI_WRAPPER)) return; bootmem_add_range((uintptr_t)_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE); diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c index 46c961e0ed..40987d8bcd 100644 --- a/src/arch/mips/bootblock_simple.c +++ b/src/arch/mips/bootblock_simple.c @@ -26,7 +26,7 @@ void main(void) /* Mainboard basic init */ bootblock_mainboard_init(); -#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE) +#if CONFIG(BOOTBLOCK_CONSOLE) console_init(); #endif diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 3238bfbf32..1e13528037 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -31,7 +31,7 @@ struct thread; struct cpu_info { struct device *cpu; unsigned long index; -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) struct thread *thread; #endif }; diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 4ee580cd96..547cb76a04 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -33,7 +33,7 @@ struct thread; struct cpu_info { struct device *cpu; unsigned long index; -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) struct thread *thread; #endif }; diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index e5408288af..a5f3fd4065 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -45,7 +45,7 @@ static uintptr_t sbi_set_timer(uint64_t when) return 0; } -#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) +#if CONFIG(CONSOLE_SERIAL) static uintptr_t sbi_console_putchar(uint8_t ch) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, ch); @@ -86,7 +86,7 @@ void handle_sbi(trapframe *tf) ret = sbi_set_timer(arg0); #endif break; -#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) +#if CONFIG(CONSOLE_SERIAL) case SBI_CONSOLE_PUTCHAR: ret = sbi_console_putchar(arg0); break; diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 623a6df2e3..486f8e34ed 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1066,7 +1066,7 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) header->checksum = acpi_checksum((void *)bert, header->length); } -#if IS_ENABLED(CONFIG_COMMON_FADT) +#if CONFIG(COMMON_FADT) void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -1088,11 +1088,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) || - IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) + if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || + CONFIG(SYSTEM_TYPE_LAPTOP)) fadt->preferred_pm_profile = PM_MOBILE; - else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) || - IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET)) + else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || + CONFIG(SYSTEM_TYPE_TABLET)) fadt->preferred_pm_profile = PM_TABLET; else fadt->preferred_pm_profile = PM_DESKTOP; @@ -1256,7 +1256,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } - if (IS_ENABLED(CONFIG_TPM1)) { + if (CONFIG(TPM1)) { printk(BIOS_DEBUG, "ACPI: * TCPA\n"); tcpa = (acpi_tcpa_t *) current; acpi_create_tcpa(tcpa); @@ -1267,7 +1267,7 @@ unsigned long write_acpi_tables(unsigned long start) } } - if (IS_ENABLED(CONFIG_TPM2)) { + if (CONFIG(TPM2)) { printk(BIOS_DEBUG, "ACPI: * TPM2\n"); tpm2 = (acpi_tpm2_t *) current; acpi_create_tpm2(tpm2); diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index c62d6f3688..c57ba48094 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -19,7 +19,7 @@ #include <arch/acpigen.h> #include <device/device.h> #include <device/path.h> -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) #include <gpio.h> #endif @@ -342,7 +342,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio) /* Pin Table, one word for each pin */ for (pin = 0; pin < gpio->pin_count; pin++) { uint16_t acpi_pin = gpio->pins[pin]; -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) acpi_pin = gpio_acpi_pin(acpi_pin); #endif acpigen_emit_word(acpi_pin); @@ -352,7 +352,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio) acpi_device_fill_from_len(resource_offset, start); /* Resource Source Name String */ -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0])); #else acpigen_emit_string(gpio->resource); diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index e455b45612..4c573033da 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -82,7 +82,7 @@ static int backup_create_or_update(struct resume_backup *backup_mem, { uintptr_t top; - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) { base = CONFIG_RAMBASE; size = HIGH_MEMORY_SAVE; } @@ -169,7 +169,7 @@ void acpi_prepare_resume_backup(void) if (!acpi_s3_resume_allowed()) return; - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + if (CONFIG(RELOCATABLE_RAMSTAGE)) return; backup_create_or_update(NULL, (uintptr_t)_program, @@ -194,7 +194,7 @@ static void acpi_jump_to_wakeup(void *vector) return; } - if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (!CONFIG(RELOCATABLE_RAMSTAGE)) { struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); if (backup_mem && backup_mem->valid) { backup_mem->valid = 0; @@ -224,7 +224,7 @@ void __weak mainboard_suspend_resume(void) void acpi_resume(void *wake_vec) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); /* Restore GNVS pointer in SMM if found */ diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 02f492cfaa..4ead9ea769 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -16,7 +16,7 @@ #include <rules.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* * This path is for stages that are post bootblock when employing @@ -43,8 +43,8 @@ _start: sub %edi, %ecx rep stosl -#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \ - || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP))) +#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ + || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) /* Wait for a JTAG debugger to break in and set EBX non-zero */ xor %ebx, %ebx @@ -55,7 +55,7 @@ debug_spinloop: #endif andl $0xfffffff0, %esp -#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) +#if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif call car_stage_entry @@ -75,7 +75,7 @@ car_stage_entry: #include <arch/x86/prologue.inc> #include <cpu/x86/32bit/entry32.inc> #include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) #include <cpu/x86/sse_enable.inc> #endif diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 5a9333413a..8ccd3e4629 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -17,7 +17,7 @@ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> #include <arch/x86/id.ld> -#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 4eb36b2ce1..ea55096abd 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -32,7 +32,7 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> -#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP) +#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ xor %ebx, %ebx @@ -44,7 +44,7 @@ debug_spinloop: bootblock_protected_mode_entry: -#if !IS_ENABLED(CONFIG_USE_MARCH_586) +#if !CONFIG(USE_MARCH_586) /* MMX registers required here */ /* BIST result in eax */ @@ -57,12 +57,12 @@ bootblock_protected_mode_entry: movd %edx, %mm2 #endif -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) enable_sse: mov %cr4, %eax or $CR4_OSFXSR, %ax mov %eax, %cr4 -#endif /* IS_ENABLED(CONFIG_SSE) */ +#endif /* CONFIG(SSE) */ /* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index bfcc1e61a9..02603e91e3 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -37,7 +37,7 @@ #include <arch/x86/timestamp.inc> -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) #include <cpu/x86/sse_enable.inc> #endif diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index bf71bca4e6..fc041c8018 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -22,12 +22,12 @@ static void main(unsigned long bist) bootblock_mainboard_init(); sanitize_cmos(); -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) cmos_post_init(); #endif } -#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) +#if CONFIG(VBOOT_SEPARATE_VERSTAGE) const char *target1 = "fallback/verstage"; #else const char *target1 = "fallback/romstage"; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ecdc7..32b848df9b 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -25,7 +25,7 @@ _stack: .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE _estack: -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) .global thread_stacks thread_stacks: .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS @@ -76,7 +76,7 @@ _start: movl $_estack, %esp andl $(~(CONFIG_STACK_SIZE-1)), %esp -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) /* Push the thread pointer. */ push $0 #endif @@ -93,7 +93,7 @@ _start: andl $0xFFFFFFF0, %esp -#if IS_ENABLED(CONFIG_GDB_WAIT) +#if CONFIG(GDB_WAIT) call gdb_hw_init call gdb_stub_breakpoint #endif @@ -104,7 +104,7 @@ _start: hlt jmp .Lhlt -#if IS_ENABLED(CONFIG_GDB_WAIT) +#if CONFIG(GDB_WAIT) .globl gdb_stub_breakpoint gdb_stub_breakpoint: diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d6576f73c4..4637362060 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -19,7 +19,7 @@ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_region_start = . ; -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ _pagetables = . ; @@ -28,7 +28,7 @@ #endif /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ -#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 16K) #endif /* Vboot measured boot TCPA log measurements. @@ -38,7 +38,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _car_stack_end = .; @@ -48,7 +48,7 @@ * multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); /* Page directory pointer table resides here. There are 4 8-byte entries * totalling 32 bytes that need to be 32-byte aligned. The reason the @@ -74,7 +74,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ _car_global_start = .; -#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if CONFIG(NO_CAR_GLOBAL_MIGRATION) /* Allow global unitialized variables when CAR_GLOBALs are not used. */ *(.bss) *(.bss.*) @@ -89,15 +89,15 @@ _car_global_end = .; _car_relocatable_data_end = .; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \ - !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \ + !CONFIG(USE_NATIVE_RAMINIT) . = ABSOLUTE(0xff7e1000); _mrc_pool = .; . += 0x5000; _emrc_pool = .; #endif -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; _car_stack_end = _car_region_end; #endif @@ -113,7 +113,7 @@ .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) -#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if !CONFIG(NO_CAR_GLOBAL_MIGRATION) *(.bss) *(.bss.*) *(.sbss) @@ -125,9 +125,9 @@ } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 73967e17f8..648633f070 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <arch/acpi.h> -#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP) +#if CONFIG(CBMEM_TOP_BACKUP) void *cbmem_top(void) { @@ -39,7 +39,7 @@ void *cbmem_top(void) /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { -#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME) /* ACPI resume needs to be cleared in the fail-to-recover case, but that * condition is only handled during ramstage. */ acpi_fail_wakeup(); diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d070dd924a..80d4d0da4a 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -284,7 +284,7 @@ void lb_arch_add_records(struct lb_header *header) struct lb_tsc_info *tsc_info; /* Don't advertise a TSC rate unless it's constant. */ - if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + if (!CONFIG(TSC_CONSTANT_RATE)) return; freq_khz = tsc_freq_mhz() * 1000; @@ -302,7 +302,7 @@ void lb_arch_add_records(struct lb_header *header) void arch_bootstate_coreboot_exit(void) { /* APs are already parked by existing infrastructure. */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + if (!CONFIG(PARALLEL_MP_AP_WORK)) return; /* APs are waiting for work. Last thing to do is park them. */ diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 700eb84cd0..b00777a455 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -22,7 +22,7 @@ #include <stdint.h> #include <string.h> -#if IS_ENABLED(CONFIG_GDB_STUB) +#if CONFIG(GDB_STUB) /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. * At least NUM_REGBYTES*2 are needed for register packets @@ -394,7 +394,7 @@ void x86_exception(struct eregs *info); void x86_exception(struct eregs *info) { -#if IS_ENABLED(CONFIG_GDB_STUB) +#if CONFIG(GDB_STUB) int signo; memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); gdb_stub_registers[PC] = info->eip; diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 735399b8b1..769a758b9d 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -61,7 +61,7 @@ _start: * 0x00: Number of variable MTRRs to clear */ -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) mov %esp, %ebp /* Need to align stack to 16 bytes at the call instruction. Therefore diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index 83ab858e22..c9aec6d111 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -40,7 +40,7 @@ static void move_gdt(int is_recovery) struct gdtarg gdtarg; /* ramstage is already in high memory. No need to use a new gdt. */ - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + if (CONFIG(RELOCATABLE_RAMSTAGE)) return; newgdt = cbmem_find(CBMEM_ID_GDT); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 63f3045ee0..f4ed7440c5 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -32,7 +32,7 @@ * The type and enable fields are common in ACPI, but the * values themselves are hardware implementation defined. */ -#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) #define SLP_EN (1 << 13) #define SLP_TYP_SHIFT 10 #define SLP_TYP (7 << SLP_TYP_SHIFT) @@ -41,7 +41,7 @@ #define SLP_TYP_S3 5 #define SLP_TYP_S4 6 #define SLP_TYP_S5 7 -#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES) +#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) #define SLP_EN (1 << 13) #define SLP_TYP_SHIFT 10 #define SLP_TYP (7 << SLP_TYP_SHIFT) @@ -776,7 +776,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -#if IS_ENABLED(CONFIG_COMMON_FADT) +#if CONFIG(COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); #endif @@ -885,8 +885,8 @@ enum { ACPI_S5, }; -#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ - || IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES) +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ + || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) /* Given the provided PM1 control register return the ACPI sleep type. */ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) { @@ -909,7 +909,7 @@ int acpi_get_gpe(int gpe); static inline int acpi_s3_resume_allowed(void) { - return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); + return CONFIG(HAVE_ACPI_RESUME); } /* Return address in reserved memory where to backup low memory @@ -919,7 +919,7 @@ static inline int acpi_s3_resume_allowed(void) */ void *acpi_backup_container(uintptr_t base, size_t size); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea761..b40dd1bc9e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -188,7 +188,7 @@ struct thread; struct cpu_info { struct device *cpu; unsigned int index; -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) struct thread *thread; #endif }; diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2b74544d5c..9ea1537d81 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -19,7 +19,7 @@ #include <arch/symbols.h> #include <stdlib.h> -#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ @@ -100,6 +100,6 @@ static inline int car_active(void) { return 0; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) -#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */ +#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */ #endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index 08aedef797..d71d5a51f4 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -32,7 +32,7 @@ #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE +#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); #else static inline void exception_init(void) { /* not implemented */ } diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 3373e8223b..086e5bc8f2 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -21,9 +21,9 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) +#if CONFIG(PCI_OPTION_ROM_RUN_REALMODE) extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)); -#elif IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#elif CONFIG(PCI_OPTION_ROM_RUN_YABEL) #include <device/oprom/yabel/biosemu.h> #else static inline void mainboard_interrupt_handlers(int intXX, diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 3e2129fa1a..017e661f14 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -21,7 +21,7 @@ static __always_inline unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where) { - if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) { + if (CONFIG(PCI_IO_CFG_EXT)) { // seg == 0 return dev >> 4 | (where & 0xff) | ((where & 0xf00) << 16); } else { @@ -77,7 +77,7 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) outl(value, 0xCFC); } -#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT) +#if !CONFIG(MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 1d3b90aa93..41275a8dc2 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -60,7 +60,7 @@ struct eregs { }; #endif // !ASSEMBLER -#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG) +#if CONFIG(COMPILER_LLVM_CLANG) #define ADDR32(opcode) opcode #else #define ADDR32(opcode) addr32 opcode diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 183d726d19..f9186787af 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -15,9 +15,9 @@ #define ARCH_SMP_SPINLOCK_H #if !defined(__PRE_RAM__) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + || CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ + || CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ + || CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h index c0dcc92bd1..7b44e0f2a6 100644 --- a/src/arch/x86/include/cf9_reset.h +++ b/src/arch/x86/include/cf9_reset.h @@ -27,7 +27,7 @@ void do_system_reset(void); void do_full_reset(void); /* Called by functions below before reset. */ -#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE) +#if CONFIG(HAVE_CF9_RESET_PREPARE) void cf9_reset_prepare(void); #else static inline void cf9_reset_prepare(void) {} diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index a3969529ca..34ab202f71 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -103,7 +103,7 @@ static void load_vectors(void *ioapic_base) ioapic_interrupts = ioapic_interrupt_count(ioapic_base); - if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) { + if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) { /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -111,7 +111,7 @@ static void load_vectors(void *ioapic_base) printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); - } else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) { + } else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) { printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 5831723466..8e073f25cf 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -62,7 +62,7 @@ SECTIONS #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> #include <arch/x86/id.ld> -#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif #endif /* ENV_BOOTBLOCK */ diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index b1dadc3e23..7d82507fd2 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -18,7 +18,7 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) +#if !CONFIG(PCI_IO_CFG_EXT) #define CONF_CMD(dev, where) (0x80000000 | ((dev)->bus->secondary << 16) | \ ((dev)->path.pci.devfn << 8) | (where & ~3)) #else diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index f705944658..194efb4ad2 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -198,9 +198,9 @@ unsigned long copy_pirq_routing_table(unsigned long addr, addr); memcpy((void *)addr, routing_table, routing_table->size); printk(BIOS_INFO, "done.\n"); - if (IS_ENABLED(CONFIG_DEBUG_PIRQ)) + if (CONFIG(DEBUG_PIRQ)) verify_copy_pirq_routing_table(addr, routing_table); - if (IS_ENABLED(CONFIG_PIRQ_ROUTE)) + if (CONFIG(PIRQ_ROUTE)) pirq_route_irqs(addr); return addr + routing_table->size; diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index a36b90058f..d62487ef88 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -106,7 +106,7 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf, void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) { - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return; postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } @@ -151,7 +151,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) finalize_load(rsl.params, pcf->stack); - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (!CONFIG(NO_STAGE_CACHE)) stage_cache_add(STAGE_POSTCAR, prog); } @@ -162,7 +162,7 @@ void run_postcar_phase(struct postcar_frame *pcf) postcar_commit_mtrrs(pcf); - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && + if (!CONFIG(NO_STAGE_CACHE) && romstage_handoff_is_resume()) { stage_cache_load_stage(STAGE_POSTCAR, &prog); /* This is here to allow platforms to pass different stack diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index fdf8ca1358..1d0ced16c9 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,7 +30,7 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -350,7 +350,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); -#if !IS_ENABLED(CONFIG_CHROMEOS) +#if !CONFIG(CHROMEOS) t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); t->bios_version = smbios_add_string(t->eos, @@ -359,12 +359,12 @@ static int smbios_write_type0(unsigned long *current, int handle) #define SPACES \ " " t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) u32 version_offset = (u32)smbios_string_table_len(t->eos); #endif t->bios_version = smbios_add_string(t->eos, SPACES); -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); @@ -390,10 +390,10 @@ static int smbios_write_type0(unsigned long *current, int handle) BIOS_CHARACTERISTICS_SELECTABLE_BOOT | BIOS_CHARACTERISTICS_UPGRADEABLE; - if (IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT)) + if (CONFIG(CARDBUS_PLUGIN_SUPPORT)) t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD; - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; @@ -402,7 +402,7 @@ static int smbios_write_type0(unsigned long *current, int handle) return len; } -#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO) +#if !CONFIG(SMBIOS_PROVIDED_BY_MOBO) const char *__weak smbios_mainboard_serial_number(void) { @@ -753,7 +753,7 @@ unsigned long smbios_write_tables(unsigned long current) handle++)); update_max(len, max_struct_size, smbios_write_type11(¤t, &handle)); - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) update_max(len, max_struct_size, elog_smbios_write_type15(¤t,handle++)); update_max(len, max_struct_size, smbios_write_type17(¤t, diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 5319c690f2..f17fb858b0 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -238,17 +238,17 @@ void arch_write_tables(uintptr_t coreboot_table) unsigned long rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ - if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + if (CONFIG(GENERATE_PIRQ_TABLE)) rom_table_end = write_pirq_table(rom_table_end); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ - if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + if (CONFIG(GENERATE_MP_TABLE)) rom_table_end = write_mptable(rom_table_end); - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) rom_table_end = write_acpi_table(rom_table_end); - if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + if (CONFIG(GENERATE_SMBIOS_TABLES)) rom_table_end = write_smbios_table(rom_table_end); sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index b5257c4c7e..5b48c23be2 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -24,7 +24,7 @@ uint64_t timestamp_get(void) int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + if (CONFIG(TSC_CONSTANT_RATE)) return tsc_freq_mhz(); /* Filling tick_freq_mhz = 0 in timestamps-table will trigger diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 0210a92202..250a72a4ce 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -27,7 +27,7 @@ #endif #if defined(IS_ENABLED) -#if IS_ENABLED(CONFIG_DEBUG_CBFS) +#if CONFIG(DEBUG_CBFS) #define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) #else #define DEBUG(x...) diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index cfe027fcc2..1a05eebd55 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -35,7 +35,7 @@ #include <stdlib.h> #include <string.h> -#if IS_ENABLED(CONFIG_COREBOOT_BUILD) +#if CONFIG(COREBOOT_BUILD) #include <console/console.h> #include <halt.h> #define printf(...) printk(BIOS_ERR, __VA_ARGS__) diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index fb00892acd..3c82f51a4f 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -127,7 +127,7 @@ int mmc_send_ext_csd(struct sd_mmc_ctrlr *ctrlr, unsigned char *ext_csd) rv = ctrlr->send_cmd(ctrlr, &cmd, &data); - if (!rv && IS_ENABLED(CONFIG_SD_MMC_TRACE)) { + if (!rv && CONFIG(SD_MMC_TRACE)) { int i, size; size = data.blocks * data.blocksize; diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index 0c89085ca7..bda8d7470c 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -168,7 +168,7 @@ int sd_mmc_enter_standby(struct storage_media *media) /* Test for SD version 2 */ err = CARD_TIMEOUT; - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD)) { + if (CONFIG(COMMONLIB_STORAGE_SD)) { err = sd_send_if_cond(media); /* Get SD card operating condition */ @@ -177,7 +177,7 @@ int sd_mmc_enter_standby(struct storage_media *media) } /* If the command timed out, we check for an MMC card */ - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) { + if (CONFIG(COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) { /* Some cards seem to need this */ sd_mmc_go_idle(media); diff --git a/src/commonlib/storage/sd_mmc.h b/src/commonlib/storage/sd_mmc.h index e37f8f4e13..f3a6e8adbd 100644 --- a/src/commonlib/storage/sd_mmc.h +++ b/src/commonlib/storage/sd_mmc.h @@ -75,12 +75,12 @@ int sd_set_partition(struct storage_media *media, /* Controller debug functions */ #define sdhc_debug(format...) \ do { \ - if (IS_ENABLED(CONFIG_SDHC_DEBUG)) \ + if (CONFIG(SDHC_DEBUG)) \ printk(BIOS_DEBUG, format); \ } while (0) #define sdhc_trace(format...) \ do { \ - if (IS_ENABLED(CONFIG_SDHC_TRACE)) \ + if (CONFIG(SDHC_TRACE)) \ printk(BIOS_DEBUG, format); \ } while (0) #define sdhc_error(format...) printk(BIOS_ERR, "ERROR: " format) @@ -88,12 +88,12 @@ int sd_set_partition(struct storage_media *media, /* Card/device debug functions */ #define sd_mmc_debug(format...) \ do { \ - if (IS_ENABLED(CONFIG_SD_MMC_DEBUG)) \ + if (CONFIG(SD_MMC_DEBUG)) \ printk(BIOS_DEBUG, format); \ } while (0) #define sd_mmc_trace(format...) \ do { \ - if (IS_ENABLED(CONFIG_SD_MMC_TRACE)) \ + if (CONFIG(SD_MMC_TRACE)) \ printk(BIOS_DEBUG, format); \ } while (0) #define sd_mmc_error(format...) printk(BIOS_ERR, "ERROR: " format) diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index fd3915f92e..8482488236 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -318,7 +318,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr, sdhc_log_command(cmd); - if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && data) { + if (CONFIG(SDHCI_BOUNCE_BUFFER) && data) { if (data->flags & DATA_FLAG_READ) { buf = data->dest; bbflags = GEN_BB_WRITE; @@ -348,7 +348,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr, sdhci_led_control(ctrlr, 0); sdhc_log_ret(ret); - if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && bbstate) + if (CONFIG(SDHCI_BOUNCE_BUFFER) && bbstate) bounce_buffer_stop(bbstate); return ret; @@ -594,7 +594,7 @@ static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr) } /* Set the new bus width */ - if (IS_ENABLED(CONFIG_SDHC_DEBUG) + if (CONFIG(SDHC_DEBUG) && ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS | ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0)))) sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width, diff --git a/src/commonlib/storage/sdhci_display.c b/src/commonlib/storage/sdhci_display.c index 68747f4b86..6545424e07 100644 --- a/src/commonlib/storage/sdhci_display.c +++ b/src/commonlib/storage/sdhci_display.c @@ -26,7 +26,7 @@ static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr) { - if (IS_ENABLED(CONFIG_SDHC_DEBUG)) { + if (CONFIG(SDHC_DEBUG)) { int bits; uint8_t host_ctrl; uint16_t host2; @@ -53,7 +53,7 @@ static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr) static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr) { - if (IS_ENABLED(CONFIG_SDHC_DEBUG)) { + if (CONFIG(SDHC_DEBUG)) { uint16_t clk_ctrl; uint32_t clock; uint32_t divisor; @@ -79,7 +79,7 @@ static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr) static void sdhci_display_voltage(struct sdhci_ctrlr *sdhci_ctrlr) { - if (IS_ENABLED(CONFIG_SDHC_DEBUG)) { + if (CONFIG(SDHC_DEBUG)) { u8 pwr_ctrl; const char *voltage; const char *voltage_table[8] = { diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index 927e12ff30..d8ff4bc729 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -70,7 +70,7 @@ static void display_capacity(struct storage_media *media, int partition_number) capacity = media->capacity[partition_number]; name = storage_partition_name(media, partition_number); separator = ""; - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && !IS_SD(media)) + if (CONFIG(COMMONLIB_STORAGE_MMC) && !IS_SD(media)) separator = ": "; /* Determine the decimal divisor for the capacity */ @@ -124,7 +124,7 @@ void storage_display_setup(struct storage_media *media) * media->write_bl_len); /* Display the partition capacities */ - if (IS_ENABLED(CONFIG_SDHC_DEBUG)) { + if (CONFIG(SDHC_DEBUG)) { for (partition_number = 0; partition_number < ARRAY_SIZE(media->capacity); partition_number++) { if (!media->capacity[partition_number]) @@ -175,9 +175,9 @@ int storage_startup(struct storage_media *media) return err; /* Increase the bus frequency */ - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media)) + if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media)) err = sd_change_freq(media); - else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) { + else if (CONFIG(COMMONLIB_STORAGE_MMC)) { err = mmc_change_freq(media); if (!err) mmc_update_capacity(media); @@ -189,9 +189,9 @@ int storage_startup(struct storage_media *media) media->caps &= ctrlr->caps; /* Increase the bus width if possible */ - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media)) + if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media)) err = sd_set_bus_width(media); - else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) + else if (CONFIG(COMMONLIB_STORAGE_MMC)) err = mmc_set_bus_width(media); if (err) return err; @@ -329,9 +329,9 @@ int storage_set_partition(struct storage_media *media, /* Select the partition */ err = -1; - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media)) + if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media)) err = sd_set_partition(media, partition_number); - else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) + else if (CONFIG(COMMONLIB_STORAGE_MMC)) err = mmc_set_partition(media, partition_number); if (err) sd_mmc_error("Invalid partition number!\n"); @@ -345,9 +345,9 @@ const char *storage_partition_name(struct storage_media *media, /* Get the partition name */ name = NULL; - if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media)) + if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media)) name = sd_partition_name(media, partition_number); - else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) + else if (CONFIG(COMMONLIB_STORAGE_MMC)) name = mmc_partition_name(media, partition_number); return name; } diff --git a/src/console/console.c b/src/console/console.c index 1a6aec1285..50ee5c30e5 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -79,7 +79,7 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) } -#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) void gdb_hw_init(void) { __gdb_hw_init(); diff --git a/src/console/init.c b/src/console/init.c index b7cc43aef2..43b499d816 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -73,7 +73,7 @@ int console_log_level(int msg_level) if (msg_level <= log_level) return CONSOLE_LOG_ALL; - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG)) + if (CONFIG(CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG)) return CONSOLE_LOG_FAST; return 0; @@ -83,10 +83,10 @@ asmlinkage void console_init(void) { init_log_level(); - if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT)) + if (CONFIG(DEBUG_CONSOLE_INIT)) car_set_var(console_inited, 1); - if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE) + if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE) pci_early_bridge_init(); console_hw_init(); diff --git a/src/console/post.c b/src/console/post.c index 08bdaa18a9..236aa8cdaa 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) #include <arch/io.h> #endif @@ -40,7 +40,7 @@ void __weak mainboard_post(uint8_t value) #define mainboard_post(x) #endif -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) DECLARE_SPIN_LOCK(cmos_post_lock) @@ -48,7 +48,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) void cmos_post_log(void) { u8 code = 0; -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) u32 extra = 0; #endif @@ -58,13 +58,13 @@ void cmos_post_log(void) switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); #endif break; case CMOS_POST_BANK_1_MAGIC: code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); #endif break; @@ -82,9 +82,9 @@ void cmos_post_log(void) default: printk(BIOS_WARNING, "POST: Unexpected post code " "in previous boot: 0x%02x\n", code); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif @@ -92,7 +92,7 @@ void cmos_post_log(void) } } -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value) { spin_lock(&cmos_post_lock); @@ -146,14 +146,14 @@ static void cmos_post_code(u8 value) void post_code(uint8_t value) { -#if !IS_ENABLED(CONFIG_NO_POST) -#if IS_ENABLED(CONFIG_CONSOLE_POST) +#if !CONFIG(NO_POST) +#if CONFIG(CONSOLE_POST) printk(BIOS_EMERG, "POST: 0x%02x\n", value); #endif -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) cmos_post_code(value); #endif -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb(value, CONFIG_POST_IO_PORT); #endif #endif diff --git a/src/console/printk.c b/src/console/printk.c index 6050620dca..09522158a7 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -26,7 +26,7 @@ #include <stddef.h> #include <trace.h> -#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) DECLARE_SPIN_LOCK(console_lock) #endif @@ -49,7 +49,7 @@ int vprintk(int msg_level, const char *fmt, va_list args) { int i, log_this; - if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM && + if (CONFIG(SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM && !boot_cpu()) return 0; @@ -59,7 +59,7 @@ int vprintk(int msg_level, const char *fmt, va_list args) DISABLE_TRACE; #ifdef __PRE_RAM__ -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) spin_lock(romstage_console_lock()); #endif #else @@ -74,7 +74,7 @@ int vprintk(int msg_level, const char *fmt, va_list args) } #ifdef __PRE_RAM__ -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) spin_unlock(romstage_console_lock()); #endif #else diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index b20c14e6a3..043a1dae37 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -20,7 +20,7 @@ #define call_tx(x) tx_byte(x, data) -#if !IS_ENABLED(CONFIG_ARCH_MIPS) +#if !CONFIG(ARCH_MIPS) #define SUPPORT_64BIT_INTS #endif diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 96d6cdc637..0693dedeb8 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -34,7 +34,7 @@ static void model_12_init(struct device *dev) msr_t msr; int num_banks; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -65,7 +65,7 @@ static void model_12_init(struct device *dev) /* Set the processor name string */ // init_processor_name(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 3086f158df..1516a6b2c6 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -33,7 +33,7 @@ static void model_14_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif printk(BIOS_DEBUG, "Model 14 Init.\n"); @@ -83,7 +83,7 @@ static void model_14_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 7528431e07..26b20dcfd4 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -37,7 +37,7 @@ static void model_15_init(struct device *dev) int num_banks; int msrno; unsigned int cpu_idx; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -82,7 +82,7 @@ static void model_15_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -102,7 +102,7 @@ static void model_15_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { cpu_idx = cpu_info()->index; printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 188f95cf08..e6fb0db6de 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -35,7 +35,7 @@ static void model_16_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -80,7 +80,7 @@ static void model_16_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index e4c2704727..f923a47db4 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -141,7 +141,7 @@ CAR_FAM10_out: CAR_FAM10_errata_applied: -#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) +#if CONFIG(MMCONF_SUPPORT) #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF) #error "MMCONF_BASE_ADDRESS too big" #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF) @@ -315,7 +315,7 @@ clear_fixed_var_mtrr_out: */ .endm -#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) +#if CONFIG(CPU_AMD_MODEL_10XXX) #if CacheSize > 0x80000 #error Invalid CAR size, must be at most 128k (processor limit is 512k). #endif diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index b1d0c5a1e1..199a453501 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -80,7 +80,7 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config) family = amd_fam1x_cpu_family(); -#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) +#if CONFIG(CPU_AMD_MODEL_10XXX) if (family >= 0x6f) { /* Family 15h or later */ diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index e55ef408f3..18e7542e6d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -36,7 +36,7 @@ #error "You need to set CONFIG_RAMTOP greater than 1M" #endif -#if IS_ENABLED(CONFIG_DEBUG_CAR) +#if CONFIG(DEBUG_CAR) #define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) #else #define print_car_debug(format, arg...) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 428924df34..db58f5dd34 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -95,21 +95,21 @@ b.- prep_fid_change(...) static inline void print_debug_fv(const char *str, u32 val) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) +#if CONFIG(SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) + #if CONFIG(SVI_HIGH_FREQ) if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) + #if CONFIG(SVI_HIGH_FREQ) if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } @@ -1036,7 +1036,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid) } -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -1055,7 +1055,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -1070,8 +1070,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) print_debug_fv("BSP fid = ", fv.common_fid); -#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ - !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) +#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ + !CONFIG(SET_FIDVID_CORE0_ONLY) /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 57d4424bb1..76bc6d99e5 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -18,7 +18,7 @@ #include <device/pci_ops.h> #include "init_cpus.h" -#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) +#if CONFIG(HAVE_OPTION_TABLE) #include "option_table.h" #endif #include <pc80/mc146818rtc.h> @@ -30,17 +30,17 @@ #include <southbridge/amd/common/reset.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) +#if CONFIG(SOUTHBRIDGE_AMD_SB700) #include <southbridge/amd/sb700/sb700.h> #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#if CONFIG(SOUTHBRIDGE_AMD_SB800) #include <southbridge/amd/sb800/sb800.h> #endif #include "cpu/amd/car/disable_cache_as_ram.c" -#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) +#if CONFIG(PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { // set the NB_CFG_MSR[46]=1; @@ -156,7 +156,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || + if (!CONFIG(LOGICAL_CPUS) || read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { @@ -186,8 +186,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, for (j = jstart; j <= jend; j++) { ap_apicid = get_boot_apic_id(i, j); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) -#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if !CONFIG(LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) return result; } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif @@ -402,17 +402,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (!is_fam15h()) set_apicid_cpuid_lo(); set_EnableCf8ExtCfg(); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) enable_apic_ext_id(id.nodeid); #endif } enable_lapic(); -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if !CONFIG(LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -424,7 +424,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) lapic_write(LAPIC_ID, dword); } -#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) +#if CONFIG(LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -477,8 +477,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) } } -#if IS_ENABLED(CONFIG_SET_FIDVID) -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) +#if CONFIG(SET_FIDVID) +#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY) // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -501,7 +501,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (is_fam15h()) { /* core 1 on node 0 is special; to avoid corrupting the * BSP do not alter MTRRs on that core */ - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1; else fam15_bsp_core1_apicid = 1; @@ -578,7 +578,7 @@ static void start_node(u8 node) /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); @@ -1040,7 +1040,7 @@ void cpuSetAMDMSR(uint8_t node_id) } } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800) if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(MSR_INTPEND); @@ -1060,7 +1060,7 @@ void cpuSetAMDMSR(uint8_t node_id) if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { enable_c_states = 0; - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) enable_c_states = !!nvram; @@ -1869,7 +1869,7 @@ void finalize_node_setup(struct sys_info *sysinfo) cpuSetAMDPCI(i); } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) // Prep each node for FID/VID setup. prep_fid_change(); #endif @@ -1883,6 +1883,6 @@ void finalize_node_setup(struct sys_info *sysinfo) #endif } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) # include "fidvid.c" #endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 674ba782d7..9819caf909 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -62,7 +62,7 @@ static void model_10xxx_init(struct device *dev) msr_t msr; int num_banks; struct node_core_id id; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif uint8_t delay_start; @@ -123,7 +123,7 @@ static void model_10xxx_init(struct device *dev) /* Set the processor name string */ init_processor_name(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -204,7 +204,7 @@ static void model_10xxx_init(struct device *dev) wrmsr(BU_CFG2_MSR, msr); } - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n"); /* Set SMM base address for this CPU */ diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index 15b655028c..d024069e30 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -187,7 +187,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) uint8_t enable_c_states; enable_c_states = 0; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) enable_c_states = !!nvram; #endif diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 344dc77d07..1433e0753f 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -44,7 +44,7 @@ static inline uint8_t is_fam15h(void) uint64_t get_uma_memory_size(uint64_t topmem) { uint64_t uma_size = 0; - if (IS_ENABLED(CONFIG_GFXUMA)) { + if (CONFIG(GFXUMA)) { /* refer to UMA Size Consideration in 780 BDG. */ if (topmem >= 0x40000000) /* 1GB and above system memory */ uma_size = 0x10000000; /* 256M recommended UMA */ diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 783675d953..584041e923 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -200,7 +200,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) } #ifdef __PRE_RAM__ -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) +#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_lock(romstage_microcode_cbfs_lock()); #endif #endif @@ -210,7 +210,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); #ifdef __PRE_RAM__ -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) +#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_unlock(romstage_microcode_cbfs_lock()); #endif #endif @@ -220,7 +220,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); #ifdef __PRE_RAM__ -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) +#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_unlock(romstage_microcode_cbfs_lock()); #endif #endif diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index ae2a2dfe88..10fd9f568c 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -88,7 +88,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (CONFIG(UDELAY_LAPIC)){ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 5455b0cf11..3a641bf07f 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -36,7 +36,7 @@ static void model_15_init(struct device *dev) int num_banks; int msrno; unsigned int cpu_idx; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -78,7 +78,7 @@ static void model_15_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -98,7 +98,7 @@ static void model_15_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { cpu_idx = cpu_info()->index; printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index e028b6f85b..2cbeab8316 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -94,7 +94,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { + if (CONFIG(UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index d156525b60..65d87c22ec 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -51,7 +51,7 @@ static void model_15_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -90,7 +90,7 @@ static void model_15_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 163066b6d8..3769319866 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -99,7 +99,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { + if (CONFIG(UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 7ae89b48e8..5678c5f58d 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -34,7 +34,7 @@ static void model_16_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -75,7 +75,7 @@ static void model_16_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 601675123e..ad4a7ead6d 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) +#if CONFIG(HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -124,7 +124,7 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores) } } -#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) +#if (!CONFIG(CPU_AMD_MODEL_10XXX)) //it is running on core0 of node0 static void start_other_cores(void) { diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 7788a2da4e..b2b915fe76 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -134,7 +134,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr -#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) +#if CONFIG(CPU_HAS_L2_ENABLE_MSR) /* * Enable the L2 cache. Currently this assumes that this * only affect socketed CPU's for which this is always valid, @@ -152,7 +152,7 @@ addrsize_set_high: invd movl %eax, %cr0 -#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) update_microcode: /* put the return address in %esp */ movl $end_microcode_update, %esp diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9d50582232..4beac0b94c 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,7 +23,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* Fixed location, ASSERTED in failover.ld if it changes. */ .set ap_sipi_vector_in_rom, 0xff #endif @@ -318,7 +318,7 @@ no_msr_11e: invd movl %eax, %cr0 -#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) update_microcode: /* put the return address in %esp */ movl $end_microcode_update, %esp diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 264ad4ab7f..a7daff4fb2 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -54,7 +54,7 @@ static void romstage_main(unsigned long bist) platform_enter_postcar(); } -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, * keeping changes in cache_as_ram.S easy to manage. */ diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index a568ea14e5..a2ff65cecc 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -31,7 +31,7 @@ void set_feature_ctrl_vmx(void) { msr_t msr; uint32_t feature_flag; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + int enable = CONFIG(ENABLE_VMX); feature_flag = cpu_get_feature_flags_ecx(); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -71,7 +71,7 @@ void set_feature_ctrl_vmx(void) void set_feature_ctrl_lock(void) { msr_t msr; - int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT); + int lock = CONFIG(SET_IA32_FC_LOCK_BIT); uint32_t feature_flag = cpu_get_feature_flags_ecx(); /* Check if VMX is supported before reading or writing the MSR */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 7994f0bb2c..efa86935f5 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -132,7 +132,7 @@ static void model_406dx_init(struct device *cpu) x86_enable_cache(); /* Load microcode */ - if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); /* Clear out pending MCEs */ diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 3a306b5729..722cc0102e 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,7 +23,7 @@ #include <cpu/intel/microcode/microcode.c> #include "haswell.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) +#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/lynxpoint/pch.h> #else diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index d5028c299b..1e5f3d3656 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -30,7 +30,7 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <northbridge/intel/haswell/haswell.h> @@ -89,7 +89,7 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); @@ -131,7 +131,7 @@ void romstage_common(const struct romstage_params *params) /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + #if CONFIG(HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ system_reset(); #endif diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index b05d3d45e1..f2f28f6377 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -19,7 +19,7 @@ #include <smp/spinlock.h> #include <assert.h> -#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) +#if CONFIG(PARALLEL_CPU_INIT) #error Intel hyper-threading requires serialized CPU init #endif diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 48909c25e9..ea2d83841f 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -75,7 +75,7 @@ static void per_cpu_smm_trigger(void) printk(BIOS_DEBUG, "SMRR status: %senabled\n", ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); } else { - if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT)) + if (!CONFIG(SET_IA32_FC_LOCK_BIT)) printk(BIOS_INFO, "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index ed528d1bdd..19dbda850a 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -23,7 +23,7 @@ #include <cpu/intel/microcode/microcode.c> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) +#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) #include <southbridge/intel/ibexpeak/pch.h> #include "model_2065x.h" #else diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 670b09750e..9dcbe372ff 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -24,8 +24,8 @@ #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) +#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ + CONFIG(SOUTHBRIDGE_INTEL_C216) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/bd82x6x/pch.h> #else diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index fc0db17a54..d348df6c82 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { + if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -37,7 +37,7 @@ static void model_f3x_init(struct device *cpu) setup_lapic(); /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 4b824a57a5..cc2a8952ca 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -175,7 +175,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) } /* Adjust available SMM handler memory size. */ - if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index c31f4c0e3b..12cbfc0b81 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h> #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED) +#if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED) static inline int get_global_turbo_state(void) { return TURBO_UNKNOWN; diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c55e9..9e00c55a92 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,8 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ + CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ @@ -44,7 +44,7 @@ _start16bit: cli /* Save the BIST result */ movl %eax, %ebp -#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_RESET_VECTOR_CORRECT) #endif diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 837bccf87a..52c07685cf 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -47,7 +47,7 @@ __protected_start: /* Save the BIST value */ movl %eax, %ebp -#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_ENTER_PROTECTED_MODE) #endif diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c index 2023aede74..7b982a629e 100644 --- a/src/cpu/x86/backup_default_smm.c +++ b/src/cpu/x86/backup_default_smm.c @@ -25,7 +25,7 @@ void *backup_default_smm_area(void) void *save_area; const void *default_smm = (void *)SMM_DEFAULT_BASE; - if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (!CONFIG(HAVE_ACPI_RESUME)) return NULL; /* diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 1a99c36d82..6fc61686df 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -20,7 +20,7 @@ #include <arch/early_variables.h> #include <symbols.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0) +#if CONFIG(PLATFORM_USES_FSP1_0) #include <drivers/intel/fsp1_0/fsp_util.h> #endif typedef void (* const car_migration_func_t)(void); @@ -61,7 +61,7 @@ void *car_get_var_ptr(void *var) return var; } -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0) +#if CONFIG(PLATFORM_USES_FSP1_0) migrated_base = (char *)find_saved_temp_mem( *(void **)CBMEM_FSP_HOB_PTR); /* FSP 1.0 migrates the entire DCACHE RAM */ @@ -96,7 +96,7 @@ void *car_sync_var_ptr(void *var) * keep console buffer in CAR until cbmemc_reinit() moves it. */ if (*mig_var == _preram_cbmem_console) { - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)) + if (CONFIG(PLATFORM_USES_FSP1_0)) *mig_var += (char *)mig_var - (char *)var; return mig_var; } @@ -142,7 +142,7 @@ static void do_car_migrate_variables(void) static void car_migrate_variables(int is_recovery) { - if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)) + if (!CONFIG(PLATFORM_USES_FSP1_0)) do_car_migrate_variables(); } ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index ea10fd0554..6521a8a308 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -98,7 +98,7 @@ void udelay(u32 usecs) } while ((start - value) < ticks); } -#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER) +#if CONFIG(LAPIC_MONOTONIC_TIMER) #include <timer.h> static struct monotonic_counter { diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 4654086114..f4c2326a0b 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -15,7 +15,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic_def.h> -#if IS_ENABLED(CONFIG_SMP) +#if CONFIG(SMP) int boot_cpu(void) { int bsp; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7daca0ac67..3ad1f0a055 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -147,9 +147,9 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \ - && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \ - && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X) +#if !CONFIG(CPU_AMD_MODEL_10XXX) \ + && !CONFIG(CPU_INTEL_MODEL_206AX) \ + && !CONFIG(CPU_INTEL_MODEL_2065X) mdelay(10); #endif @@ -320,7 +320,7 @@ int start_cpu(struct device *cpu) return result; } -#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT) +#if CONFIG(AP_IN_SIPI_WAIT) /** * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of @@ -408,7 +408,7 @@ asmlinkage void secondary_cpu_init(unsigned int index) { atomic_inc(&active_cpus); - if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + if (!CONFIG(PARALLEL_CPU_INIT)) spin_lock(&start_cpu_lock); #ifdef __SSE3__ @@ -423,7 +423,7 @@ asmlinkage void secondary_cpu_init(unsigned int index) #endif cpu_initialize(index); - if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + if (!CONFIG(PARALLEL_CPU_INIT)) spin_unlock(&start_cpu_lock); atomic_dec(&active_cpus); @@ -440,7 +440,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) continue; - if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu)) + if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu)) continue; if (!cpu->enabled) @@ -454,7 +454,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) printk(BIOS_ERR, "CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); - if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + if (!CONFIG(PARALLEL_CPU_INIT)) udelay(10); } @@ -554,24 +554,24 @@ void initialize_cpus(struct bus *cpu_bus) if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) + if (!CONFIG(SERIALIZED_SMM_INITIALIZATION)) smm_init(); /* start all aps at first, so we can init ECC all together */ - if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT)) start_other_cpus(cpu_bus, info->cpu); /* Initialize the bootstrap processor */ cpu_initialize(0); - if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT)) start_other_cpus(cpu_bus, info->cpu); /* Now wait the rest of the cpus stop*/ if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) { + if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) { /* At this point, all APs are sleeping: * smm_init() will queue a pending SMI on all cpus * and smm_other_cpus() will start them one by one */ @@ -589,7 +589,7 @@ void initialize_cpus(struct bus *cpu_bus) recover_lowest_1M(); } -#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if !CONFIG(HAVE_SMI_HANDLER) /* Empty stubs for platforms without SMI handlers. */ void smm_init(void) { diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d28e..2057df011f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -714,7 +714,7 @@ struct mp_state { static int is_smm_enabled(void) { - return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm; + return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm; } static void smm_disable(void) @@ -724,7 +724,7 @@ static void smm_disable(void) static void smm_enable(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) mp_state.do_smm = 1; } @@ -891,7 +891,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us) struct stopwatch sw; int cur_cpu = cpu_index(); - if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) { + if (!CONFIG(PARALLEL_MP_AP_WORK)) { printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); return -1; } @@ -933,7 +933,7 @@ static void ap_wait_for_instruction(void) struct mp_callback **per_cpu_slot; int cur_cpu; - if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + if (!CONFIG(PARALLEL_MP_AP_WORK)) return; cur_cpu = cpu_index(); @@ -1028,7 +1028,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) * Default to smm_initiate_relocation() if trigger callback isn't * provided. */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && + if (CONFIG(HAVE_SMI_HANDLER) && ops->per_cpu_smm_trigger == NULL) mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; } diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index c562d84941..c430bc1e8f 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -197,6 +197,6 @@ static void _display_mtrrs(void) asmlinkage void display_mtrrs(void) { - if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + if (CONFIG(DISPLAY_MTRRS)) _display_mtrrs(); } diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index b45d17f010..d87c3d43d3 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,7 @@ #include <memrange.h> #include <cpu/amd/mtrr.h> #include <assert.h> -#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) +#if CONFIG(X86_AMD_FIXED_MTRRS) #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else #define MTRR_FIXED_WRBACK_BITS 0 @@ -86,7 +86,7 @@ void fixed_mtrrs_expose_amd_rwdram(void) { msr_t syscfg; - if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)) + if (!CONFIG(X86_AMD_FIXED_MTRRS)) return; syscfg = rdmsr(SYSCFG_MSR); @@ -98,7 +98,7 @@ void fixed_mtrrs_hide_amd_rwdram(void) { msr_t syscfg; - if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)) + if (!CONFIG(X86_AMD_FIXED_MTRRS)) return; syscfg = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index a7e4522943..11f0c2476a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -172,7 +172,7 @@ microcode_done: test %ebx, %ebx jz 1f -#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) +#if CONFIG(X86_AMD_FIXED_MTRRS) /* Allow modification of RdDram and WrDram bits */ mov $SYSCFG_MSR, %ecx rdmsr @@ -189,7 +189,7 @@ load_msr: dec %ebx jnz load_msr -#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) +#if CONFIG(X86_AMD_FIXED_MTRRS) mov $SYSCFG_MSR, %ecx rdmsr and $~SYSCFG_MSR_MtrrFixDramModEn, %eax @@ -202,7 +202,7 @@ load_msr: and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax mov %eax, %cr0 -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) /* Enable sse instructions. */ mov %cr4, %eax orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 8c65cbd828..0ffa46537c 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -186,7 +186,7 @@ void smi_handler(u32 smm_revision) /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) spi_init(); #endif do_driver_init = 0; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9af965208..0d9abc5763 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,7 +18,7 @@ #include <cpu/x86/smm.h> #include <rmodule.h> -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -161,7 +161,7 @@ asmlinkage void smm_handler_start(void *arg) /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) spi_init(); #endif do_driver_init = 0; @@ -180,7 +180,7 @@ asmlinkage void smm_handler_start(void *arg) expected_canary); // Don't die if we can't indicate an error. - if (IS_ENABLED(CONFIG_DEBUG_SMI)) + if (CONFIG(DEBUG_SMI)) die("SMM Handler caused a stack overflow\n"); } diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6c166454dc..80b2c27c79 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -346,7 +346,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) return -1; /* Clear SMM region */ - if (IS_ENABLED(CONFIG_DEBUG_SMI)) + if (CONFIG(DEBUG_SMI)) memset(smram, 0xcd, size); total_stack_size = params->per_cpu_stack_size * @@ -370,7 +370,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) base += alignment_size; } - if (IS_ENABLED(CONFIG_SSE)) { + if (CONFIG(SSE)) { fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; /* FXSAVE area below all the stacks stack. */ fxsave_area = params->stack_top; diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 06c7fa4e7f..f586b35154 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -77,7 +77,7 @@ #endif .global smm_handler_start smm_handler_start: -#if IS_ENABLED(CONFIG_SMM_LAPIC_REMAP_MITIGATION) +#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) /* Check if the LAPIC register block overlaps with SMM. * This block needs to work without data accesses because they * may be routed into the LAPIC register block. @@ -139,7 +139,7 @@ untampered_lapic: /* This is an ugly hack, and we should find a way to read the CPU index * without relying on the LAPIC ID. */ -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) +#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN) /* LAPIC IDs start from 0x10; map that to the proper core index */ subl $0x10, %ecx #endif diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index fa49def1ad..c282904de9 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -21,9 +21,9 @@ // can it be cleaned up so this include is not required? // It's needed right now because we get our DEFAULT_PMBASE from // here. -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX) #include <southbridge/intel/i82801dx/i82801dx.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX) #include <southbridge/intel/i82801ix/i82801ix.h> #else #error "Southbridge needs SMM handler support." @@ -32,7 +32,7 @@ // ADDR32() macro #include <arch/registers.h> -#if IS_ENABLED(CONFIG_SMM_TSEG) +#if CONFIG(SMM_TSEG) #error "Don't use this file with TSEG." #endif /* CONFIG_SMM_TSEG */ @@ -154,7 +154,7 @@ smm_relocate: /* End of southbridge specific section. */ -#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION) +#if CONFIG(DEBUG_SMM_RELOCATION) /* print [SMM-x] so we can determine if CPUx went to SMM */ movw $CONFIG_TTYS0_BASE, %dx mov $'[', %al diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index a589cdb8dd..0784822b30 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -98,7 +98,7 @@ bad_ctc: static unsigned long calibrate_tsc(void) { - if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + if (CONFIG(TSC_CONSTANT_RATE)) return tsc_freq_mhz(); else return calibrate_tsc_with_pit(); @@ -135,7 +135,7 @@ void udelay(unsigned int us) } } -#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER) +#if CONFIG(TSC_MONOTONIC_TIMER) #include <timer.h> static struct monotonic_counter { diff --git a/src/device/device.c b/src/device/device.c index 527298ce16..ae0dbdb1d7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -45,7 +45,7 @@ #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) #include <arch/ebda.h> #endif #include <timer.h> @@ -99,7 +99,7 @@ void dev_finalize_chips(void) DECLARE_SPIN_LOCK(dev_lock) -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) /* IGD UMA memory */ uint64_t uma_memory_base = 0; uint64_t uma_memory_size = 0; @@ -1129,7 +1129,7 @@ static void init_dev(struct device *dev) return; if (!dev->initialized && dev->ops && dev->ops->init) { -#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) +#if CONFIG(HAVE_MONOTONIC_TIMER) struct stopwatch sw; stopwatch_init(&sw); #endif @@ -1141,7 +1141,7 @@ static void init_dev(struct device *dev) printk(BIOS_DEBUG, "%s init ...\n", dev_path(dev)); dev->initialized = 1; dev->ops->init(dev); -#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) +#if CONFIG(HAVE_MONOTONIC_TIMER) printk(BIOS_DEBUG, "%s init finished in %ld usecs\n", dev_path(dev), stopwatch_duration_usecs(&sw)); #endif @@ -1177,12 +1177,12 @@ void dev_initialize(void) printk(BIOS_INFO, "Initializing devices...\n"); -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) /* * Initialize EBDA area in ramstage if early * initialization is not done. */ - if (!IS_ENABLED(CONFIG_EARLY_EBDA_INIT)) + if (!CONFIG(EARLY_EBDA_INIT)) /* Ensure EBDA is prepared before Option ROMs. */ setup_default_ebda(); #endif diff --git a/src/device/device_const.c b/src/device/device_const.c index f60f749c49..6ce1d18c93 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -191,7 +191,7 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) * due tue complicated devicetree with topology * being manipulated on-the-fly. */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)) + if (CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) return dev_find_slot(0, devfn); pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); diff --git a/src/device/oprom/include/io.h b/src/device/oprom/include/io.h index 3a723bd056..09e25f031a 100644 --- a/src/device/oprom/include/io.h +++ b/src/device/oprom/include/io.h @@ -14,7 +14,7 @@ #ifndef __OPROM_IO_H__ #define __OPROM_IO_H__ -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) #include <arch/io.h> #else void outb(u8 val, u16 port); diff --git a/src/device/oprom/include/x86emu/fpu_regs.h b/src/device/oprom/include/x86emu/fpu_regs.h index a9b4893801..a872e19896 100644 --- a/src/device/oprom/include/x86emu/fpu_regs.h +++ b/src/device/oprom/include/x86emu/fpu_regs.h @@ -102,7 +102,7 @@ struct x86_fpu_registers { #endif /* X86_FPU_SUPPORT */ -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 51e9719b3c..7640c78896 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -278,7 +278,7 @@ typedef struct { u32 mode; volatile int intr; /* mask of pending interrupts */ volatile int debug; -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) int check; u16 saved_ip; u16 saved_cs; diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index a5d436af94..fa23e55cd3 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -43,7 +43,7 @@ #include <stddef.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) #define DEBUG #endif @@ -153,7 +153,7 @@ void X86EMU_setMemBase(void *base, size_t size); void X86EMU_exec(void); void X86EMU_halt_sys(void); -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) #define HALT_SYS() \ printf("halt_sys: in %s\n", __func__); \ X86EMU_halt_sys(); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 0b19d79269..a7631a1a84 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -212,7 +212,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } -#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) +#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) vbe_mode_info_t mode_info; static int mode_info_valid; @@ -268,7 +268,7 @@ void vbe_set_graphics(void) } vbe_set_mode(&mode_info); -#if IS_ENABLED(CONFIG_BOOTSPLASH) +#if CONFIG(BOOTSPLASH) struct jpeg_decdata *decdata; unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, @@ -349,7 +349,7 @@ void run_bios(struct device *dev, unsigned long addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) +#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif @@ -383,7 +383,7 @@ int asmlinkage interrupt_handler(u32 intnumber, cs = cs_ip >> 16; flags = stackflags; -#if IS_ENABLED(CONFIG_REALMODE_DEBUG) +#if CONFIG(REALMODE_DEBUG) printk(BIOS_DEBUG, "oprom: INT# 0x%x\n", intnumber); printk(BIOS_DEBUG, "oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", eax, ebx, ecx, edx); diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 3600200d39..2629ab9166 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -210,7 +210,7 @@ int int1a_handler(void) break; } -#if IS_ENABLED(CONFIG_REALMODE_DEBUG) +#if CONFIG(REALMODE_DEBUG) printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, X86_ECX); #endif diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index a77157f077..1c94d92230 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -52,7 +52,7 @@ #include <device/device.h> #include "compat/rtas.h" -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) +#if CONFIG(X86EMU_DEBUG_TIMINGS) struct mono_time zero; #endif @@ -87,44 +87,44 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad { u8 *rom_image; int i = 0; -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) debug_flags = 0; -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_JMP) +#if CONFIG(X86EMU_DEBUG_JMP) debug_flags |= DEBUG_JMP; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TRACE) +#if CONFIG(X86EMU_DEBUG_TRACE) debug_flags |= DEBUG_TRACE_X86EMU; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PNP) +#if CONFIG(X86EMU_DEBUG_PNP) debug_flags |= DEBUG_PNP; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_DISK) +#if CONFIG(X86EMU_DEBUG_DISK) debug_flags |= DEBUG_DISK; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PMM) +#if CONFIG(X86EMU_DEBUG_PMM) debug_flags |= DEBUG_PMM; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_VBE) +#if CONFIG(X86EMU_DEBUG_VBE) debug_flags |= DEBUG_VBE; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INT10) +#if CONFIG(X86EMU_DEBUG_INT10) debug_flags |= DEBUG_PRINT_INT10; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INTERRUPTS) +#if CONFIG(X86EMU_DEBUG_INTERRUPTS) debug_flags |= DEBUG_INTR; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) +#if CONFIG(X86EMU_DEBUG_CHECK_VMEM_ACCESS) debug_flags |= DEBUG_CHECK_VMEM_ACCESS; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_MEM) +#if CONFIG(X86EMU_DEBUG_MEM) debug_flags |= DEBUG_MEM; #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_IO) +#if CONFIG(X86EMU_DEBUG_IO) debug_flags |= DEBUG_IO; #endif #endif -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) +#if CONFIG(X86EMU_DEBUG_TIMINGS) /* required for i915tool compatible output */ zero.microseconds = 0; #endif @@ -345,7 +345,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad * some boot device status in AX (see PNP BIOS Spec Section 3.3 */ DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX); -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) DEBUG_PRINTF("Exit Status Decode:\n"); if (M.x86.R_AX & 0x100) { // bit 8 DEBUG_PRINTF diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 1cebdf0a5a..fa1b6b7cf6 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -45,7 +45,7 @@ #define VMEM_SIZE (1024 * 1024) /* 1 MB */ -#if !IS_ENABLED(CONFIG_YABEL_DIRECTHW) +#if !CONFIG(YABEL_DIRECTHW) #if CONFIG_YABEL_VIRTMEM_LOCATION u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION; #else @@ -63,7 +63,7 @@ void run_bios(struct device * dev, unsigned long addr) biosemu(vmem, VMEM_SIZE, dev, addr); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) +#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) vbe_set_graphics(); #endif } @@ -73,7 +73,7 @@ unsigned long tb_freq = 0; u64 get_time(void) { u64 act = 0; -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) u32 eax, edx; __asm__ __volatile__( diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index 20db26127b..d93fc6e4c1 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -37,7 +37,7 @@ #include <timer.h> #include <types.h> -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) +#if CONFIG(X86EMU_DEBUG_TIMINGS) extern struct mono_time zero; #endif extern u32 debug_flags; @@ -91,7 +91,7 @@ static inline void set_ci(void) {}; // set to enable tracing of JMPs in x86emu #define DEBUG_JMP 0x2000 -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) #define CHECK_DBG(_flag) if (debug_flags & _flag) @@ -99,7 +99,7 @@ static inline void set_ci(void) {}; // prints the CS:IP before the printout, NOTE: actually its CS:IP of the _next_ instruction // to be executed, since the x86emu advances CS:IP _before_ actually executing an instruction -#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) +#if CONFIG(X86EMU_DEBUG_TIMINGS) #define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("[%08lx]%x:%x ", (current_time_from(&zero)).microseconds, M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x); #else #define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("%x:%x ", M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x); diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 438485effb..4a50068faf 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -58,7 +58,7 @@ typedef struct { u64 size; } __packed assigned_address_t; -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) /* coreboot version */ static void @@ -131,7 +131,7 @@ biosemu_dev_get_addr_info(void) } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) //dump translate_address_array printf("translate_address_array:\n"); translate_address_t ta; @@ -215,7 +215,7 @@ biosemu_dev_get_addr_info(void) } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) //dump translate_address_array printf("translate_address_array:\n"); translate_address_t ta; @@ -247,7 +247,7 @@ biosemu_add_special_memory(u32 start, u32 size) translate_address_array[taa_index].address_offset = 0; } -#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL) // to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF) // we look for the first prefetchable memory BAR, if no prefetchable BAR found, // we use the first memory BAR @@ -309,7 +309,7 @@ biosemu_dev_get_device_vendor_id(void) { u32 pci_config_0; -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_config_0 = pci_read_config32(bios_device.dev, 0x0); #else pci_config_0 = @@ -371,7 +371,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), sizeof(pci_ds)); clr_ci(); -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) DEBUG_PRINTF("PCI Data Structure @%lx:\n", rom_base_addr + pci_ds_offset); dump((void *) &pci_ds, sizeof(pci_ds)); @@ -435,7 +435,7 @@ biosemu_dev_init(struct device * device) DEBUG_PRINTF("%s\n", __func__); memset(&bios_device, 0, sizeof(bios_device)); -#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL) bios_device.ihandle = of_open(device_name); if (bios_device.ihandle == 0) { DEBUG_PRINTF("%s is no valid device!\n", device_name); @@ -446,7 +446,7 @@ biosemu_dev_init(struct device * device) bios_device.dev = device; #endif biosemu_dev_get_addr_info(); -#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL) biosemu_dev_find_vmem_addr(); biosemu_dev_get_puid(); #endif @@ -463,7 +463,7 @@ biosemu_dev_translate_address(int type, unsigned long * addr) { int i = 0; translate_address_t ta; -#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL) /* we don't need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index f67a388300..8e8450a1ed 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -83,7 +83,7 @@ typedef struct { typedef struct { u8 bus; u8 devfn; -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) struct device* dev; #else u64 puid; @@ -105,7 +105,7 @@ typedef struct { } biosemu_device_t; typedef struct { -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) unsigned long info; #else u8 info; @@ -149,7 +149,7 @@ u8 biosemu_dev_translate_address(int type, unsigned long * addr); static inline void out32le(void *addr, u32 val) { -#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) +#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM) *((u32*) addr) = cpu_to_le32(val); #else asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -160,7 +160,7 @@ static inline u32 in32le(void *addr) { u32 val; -#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) +#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM) val = cpu_to_le32(*((u32 *) addr)); #else asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr)); @@ -171,7 +171,7 @@ in32le(void *addr) static inline void out16le(void *addr, u16 val) { -#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) +#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM) *((u16*) addr) = cpu_to_le16(val); #else asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -182,7 +182,7 @@ static inline u16 in16le(void *addr) { u16 val; -#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) +#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM) val = cpu_to_le16(*((u16*) addr)); #else asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr)); diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 67abe81aa5..ea2a8036aa 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -362,7 +362,7 @@ handleInt1a(void) DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); /* FixME: support SI != 0 */ -#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) +#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != 0) { DEBUG_PRINTF_INTR @@ -403,7 +403,7 @@ handleInt1a(void) offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) +#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); @@ -427,7 +427,7 @@ handleInt1a(void) switch (M.x86.R_AX) { case 0xb108: M.x86.R_CL = -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. @@ -442,7 +442,7 @@ handleInt1a(void) break; case 0xb109: M.x86.R_CX = -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. @@ -457,7 +457,7 @@ handleInt1a(void) break; case 0xb10a: M.x86.R_ECX = -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. @@ -495,7 +495,7 @@ handleInt1a(void) } else { switch (M.x86.R_AX) { case 0xb10b: -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, @@ -507,7 +507,7 @@ handleInt1a(void) M.x86.R_CL); break; case 0xb10c: -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, @@ -519,7 +519,7 @@ handleInt1a(void) M.x86.R_CX); break; case 0xb10d: -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index b50a2f1cf8..7117a6eed4 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -47,7 +47,7 @@ #include <arch/io.h> -#if IS_ENABLED(CONFIG_YABEL_DIRECTHW) +#if CONFIG(YABEL_DIRECTHW) u8 my_inb(X86EMU_pioAddr addr) { u8 val; @@ -426,7 +426,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) +#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", __func__, dev_path(dev)); @@ -446,7 +446,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) HALT_SYS(); return 0; } else { -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -495,11 +495,11 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) printf ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", bus, devfn >> 3, devfn & 7, offs); -#if !IS_ENABLED(CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) +#if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) HALT_SYS(); #endif } else { -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) switch (size) { case 1: pci_write_config8(bios_device.dev, offs, val); diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index 49b6c4f9b3..fa6959e0e4 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -41,10 +41,10 @@ #include "compat/time.h" #include <device/resource.h> -#if !IS_ENABLED(CONFIG_YABEL_DIRECTHW) || !IS_ENABLED(CONFIG_YABEL_DIRECTHW) +#if !CONFIG(YABEL_DIRECTHW) || !CONFIG(YABEL_DIRECTHW) // define a check for access to certain (virtual) memory regions (interrupt handlers, BIOS Data Area, ...) -#if IS_ENABLED(CONFIG_X86EMU_DEBUG) +#if CONFIG(X86EMU_DEBUG) static u8 in_check = 0; // to avoid recursion... static inline void DEBUG_CHECK_VMEM_READ(u32 _addr, u32 _rval) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 872ca15fbc..682bf00ba5 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -34,7 +34,7 @@ #include <string.h> #include <types.h> -#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) +#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) #include <boot/coreboot_tables.h> #endif @@ -66,7 +66,7 @@ u8 *vbe_info_buffer = 0; u8 *biosmem; u32 biosmem_size; -#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) +#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static inline u8 vbe_prepare(void) { @@ -734,7 +734,7 @@ void vbe_set_graphics(void) vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -#if IS_ENABLED(CONFIG_BOOTSPLASH) +#if CONFIG(BOOTSPLASH) unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 2233ddca67..86c72b89ff 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -745,7 +745,7 @@ static int should_run_oprom(struct device *dev) if (should_run >= 0) return should_run; - if (IS_ENABLED(CONFIG_ALWAYS_RUN_OPROM)) { + if (CONFIG(ALWAYS_RUN_OPROM)) { should_run = 1; return should_run; } @@ -755,7 +755,7 @@ static int should_run_oprom(struct device *dev) */ should_run = display_init_required(); - if (!should_run && IS_ENABLED(CONFIG_CHROMEOS)) + if (!should_run && CONFIG(CHROMEOS)) should_run = vboot_wants_oprom(); if (!should_run) @@ -768,10 +768,10 @@ static int should_load_oprom(struct device *dev) /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + if (!CONFIG(S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + if (CONFIG(ALWAYS_LOAD_OPROM)) return 1; if (should_run_oprom(dev)) return 1; @@ -784,7 +784,7 @@ void pci_dev_init(struct device *dev) { struct rom_header *rom, *ram; - if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) + if (!CONFIG(VGA_ROM_RUN)) return; /* Only execute VGA ROMs. */ @@ -822,7 +822,7 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = pci_rom_write_acpi_tables, .acpi_fill_ssdt_generator = pci_rom_ssdt, #endif @@ -864,7 +864,7 @@ struct device_operations default_pci_ops_bus = { */ static struct device_operations *get_pci_bridge_ops(struct device *dev) { -#if IS_ENABLED(CONFIG_PCIX_PLUGIN_SUPPORT) +#if CONFIG(PCIX_PLUGIN_SUPPORT) unsigned int pcixpos; pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (pcixpos) { @@ -872,7 +872,7 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev) return &default_pcix_ops_bus; } #endif -#if IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) +#if CONFIG(HYPERTRANSPORT_PLUGIN_SUPPORT) unsigned int htpos = 0; while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; @@ -885,7 +885,7 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev) } } #endif -#if IS_ENABLED(CONFIG_PCIEXP_PLUGIN_SUPPORT) +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) unsigned int pciexpos; pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (pciexpos) { @@ -975,7 +975,7 @@ static void set_pci_ops(struct device *dev) goto bad; dev->ops = get_pci_bridge_ops(dev); break; -#if IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT) +#if CONFIG(CARDBUS_PLUGIN_SUPPORT) case PCI_HEADER_TYPE_CARDBUS: dev->ops = &default_cardbus_ops_bus; break; @@ -1534,7 +1534,7 @@ int get_pci_irq_pins(struct device *dev, struct device **parent_bdg) return target_pin; } -#if IS_ENABLED(CONFIG_PC80_SYSTEM) +#if CONFIG(PC80_SYSTEM) /** * Assign IRQ numbers. * @@ -1583,7 +1583,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, printk(BIOS_DEBUG, " Readback = %d\n", irq); #endif -#if IS_ENABLED(CONFIG_PC80_SYSTEM) +#if CONFIG(PC80_SYSTEM) /* Change to level triggered. */ i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED); diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a3056a..2dbfb51b5f 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -55,7 +55,7 @@ struct rom_header *pci_rom_probe(struct device *dev) if (rom_header) { printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); - } else if (!IS_ENABLED(CONFIG_ON_DEVICE_ROM_LOAD)) { + } else if (!CONFIG(ON_DEVICE_ROM_LOAD)) { printk(BIOS_DEBUG, "PCI Option ROM loading disabled " "for %s\n", dev_path(dev)); return NULL; @@ -65,7 +65,7 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86) +#if CONFIG(BOARD_EMULATION_QEMU_X86) if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else @@ -151,7 +151,7 @@ struct rom_header *pci_rom_load(struct device *dev, * devices have a mismatch between the hardware and the ROM. */ if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { -#if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if !CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif @@ -174,7 +174,7 @@ struct rom_header *pci_rom_load(struct device *dev, } /* ACPI */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) /* VBIOS may be modified after oprom init so use the copy if present. */ static struct rom_header *check_initialized(struct device *dev) @@ -182,7 +182,7 @@ static struct rom_header *check_initialized(struct device *dev) struct rom_header *run_rom; struct pci_data *rom_data; - if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) + if (!CONFIG(VGA_ROM_RUN)) return NULL; run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 44b5100742..c20981625e 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -426,19 +426,19 @@ static void pciexp_tune_dev(struct device *dev) return; /* Check for and enable Common Clock */ - if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK)) + if (CONFIG(PCIEXP_COMMON_CLOCK)) pciexp_enable_common_clock(root, root_cap, dev, cap); /* Check if per port CLK req is supported by endpoint*/ - if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM)) + if (CONFIG(PCIEXP_CLK_PM)) pciexp_enable_clock_power_pm(dev, cap); /* Enable L1 Sub-State when both root port and endpoint support */ - if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + if (CONFIG(PCIEXP_L1_SUB_STATE)) pciexp_config_L1_sub_state(root, dev); /* Check for and enable ASPM */ - if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) + if (CONFIG(PCIEXP_ASPM)) pciexp_enable_aspm(root, root_cap, dev, cap); } diff --git a/src/device/root_device.c b/src/device/root_device.c index e006bf9137..f8e2907ce4 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -150,7 +150,7 @@ static void root_dev_reset(struct bus *bus) board_reset(); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *root_dev_acpi_name(const struct device *dev) { return "\\_SB"; @@ -171,7 +171,7 @@ struct device_operations default_dev_ops_root = { .init = DEVICE_NOOP, .scan_bus = root_dev_scan_bus, .reset_bus = root_dev_reset, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = root_dev_acpi_name, #endif }; diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c index 391345d4fe..4cafacf24d 100644 --- a/src/drivers/amd/agesa/acpi_tables.c +++ b/src/drivers/amd/agesa/acpi_tables.c @@ -22,9 +22,9 @@ /* Fields were removed from the structure and we cannot add them back * without new builds of the binaryPI blobs. */ -#if !IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) +#if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \ + CONFIG(NORTHBRIDGE_AMD_PI_00630F01) || \ + CONFIG(NORTHBRIDGE_AMD_PI_00730F01) #define HAS_ACPI_SRAT TRUE #define HAS_ACPI_SLIT TRUE diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 09302d7d0e..4f0bb3fd75 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -107,7 +107,7 @@ _cache_as_ram_setup: pushl %eax call romstage_main -#if IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if CONFIG(POSTCAR_STAGE) /* We do not return. Execution continues with run_postcar_phase() * calling to chipset_teardown_car below. @@ -138,7 +138,7 @@ chipset_teardown_car: /* Register %esp is preserved in AMD_DISABLE_STACK. */ AMD_DISABLE_STACK -#if IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if CONFIG(POSTCAR_STAGE) jmp *%esp diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index fe5101fc91..92ccff8b73 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -25,9 +25,9 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/dimmSpd.h> -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI) -#if IS_ENABLED(CONFIG_ARCH_ROMSTAGE_X86_64) || \ - IS_ENABLED(CONFIG_ARCH_RAMSTAGE_X86_64) +#if CONFIG(NORTHBRIDGE_AMD_PI) +#if CONFIG(ARCH_ROMSTAGE_X86_64) || \ + CONFIG(ARCH_RAMSTAGE_X86_64) #error "FIXME: CALLOUT_ENTRY is UINT32 Data, not UINT Data" #endif #endif diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index cc65652033..6cfcde520b 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -48,7 +48,7 @@ static const char *HeapStatusStr[] = { const char *agesa_struct_name(int state) { -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) return undefined; diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 2a76b69e59..a38696fc0f 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -26,7 +26,7 @@ #define BIOS_HEAP_SIZE 0x30000 #define BIOS_HEAP_START_ADDRESS 0x010000000 -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE) +#if CONFIG(HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE) #error Increase HIGH_MEMORY_SCRATCH allocation #endif diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index ad193e15d8..586189b406 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -31,7 +31,7 @@ typedef enum { #define S3_DATA_MTRR_SIZE 0x1000 #define S3_DATA_NONVOLATILE_SIZE 0x1000 -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ +#if CONFIG(HAVE_ACPI_RESUME) && \ (S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE #error "Please increase the value of S3_DATA_SIZE" #endif @@ -94,7 +94,7 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock) static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) { -#if IS_ENABLED(CONFIG_SPI_FLASH) +#if CONFIG(SPI_FLASH) struct spi_flash flash; spi_init(); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 9b4c50a15e..d5b20b76f9 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -#if !IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if !CONFIG(POSTCAR_STAGE) #error "Only POSTCAR_STAGE is supported." #endif #if HAS_LEGACY_WRAPPER diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 15ea211f4b..c6e36b2259 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -29,7 +29,7 @@ #include <AMD.h> -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) #include "Dispatcher.h" #endif @@ -40,7 +40,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader) { -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) const char ModuleIdentifier[] = AGESA_ID; const void *agesa, *image; size_t file_size; @@ -62,7 +62,7 @@ void agesa_set_interface(struct sysinfo *cb) cb->StdHeader.CalloutPtr = GetBiosCallout; - if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)) { + if (CONFIG(CPU_AMD_AGESA_BINARY_PI)) { agesa_locate_image(&cb->StdHeader); AMD_IMAGE_HEADER *image = (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; @@ -78,10 +78,10 @@ AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, { MODULE_ENTRY dispatcher; -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) dispatcher = AmdAgesaDispatcher; #endif -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr; AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset; dispatcher = module->ModuleDispatcher; @@ -339,7 +339,7 @@ static void amd_bs_dev_enable(void *arg) agesa_execute_state(cb, AMD_INIT_MID); /* FIXME */ - if (IS_ENABLED(CONFIG_AMD_SB_CIMX) && acpi_is_wakeup_s3()) + if (CONFIG(AMD_SB_CIMX) && acpi_is_wakeup_s3()) sb_After_Pci_Restore_Init(); } diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index fd86f39065..97d7098eeb 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -26,7 +26,7 @@ * This can either be declared as part of the option * table or statically defined in the board config. */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) # include "option_table.h" # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) #else diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 0d16b2bed5..85b79983a5 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -13,14 +13,14 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif #include <arch/early_variables.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) #include <pc80/mc146818rtc.h> #endif #include <bcd.h> @@ -36,7 +36,7 @@ #include "elog_internal.h" -#if IS_ENABLED(CONFIG_ELOG_DEBUG) +#if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) #else #define elog_debug(STR...) @@ -207,7 +207,7 @@ static void elog_debug_dump_buffer(const char *msg) struct region_device *rdev; void *buffer; - if (!IS_ENABLED(CONFIG_ELOG_DEBUG)) + if (!CONFIG(ELOG_DEBUG)) return; elog_debug(msg); @@ -628,7 +628,7 @@ static inline u8 *elog_flash_offset_to_address(void) struct elog_state *es = car_get_var_ptr(&g_elog_state); /* Only support memory-mapped devices. */ - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return NULL; if (!region_device_sz(&es->nv_dev)) @@ -651,7 +651,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) struct elog_state *es = car_get_var_ptr(&g_elog_state); size_t elog_size = region_device_sz(&es->nv_dev); - if (IS_ENABLED(CONFIG_ELOG_CBMEM)) { + if (CONFIG(ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ void *cbmem = cbmem_add(CBMEM_ID_ELOG, elog_size); if (cbmem) @@ -790,7 +790,7 @@ static bool elog_do_add_boot_count(void) if (ENV_SMM) return false; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) return !acpi_is_wakeup_s3(); #else return true; @@ -802,9 +802,9 @@ static void ramstage_elog_add_boot_count(void) if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) /* Check and log POST codes from previous boot */ - if (IS_ENABLED(CONFIG_CMOS_POST)) + if (CONFIG(CMOS_POST)) cmos_post_log(); #endif } @@ -869,7 +869,7 @@ int elog_init(void) */ static void elog_fill_timestamp(struct event_header *event) { -#if IS_ENABLED(CONFIG_RTC) +#if CONFIG(RTC) struct rtc_time time; rtc_get(&time); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index cdd2c20f5a..de3feac20e 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -135,9 +135,9 @@ static void bochs_init_text_mode(struct device *dev) static void bochs_init(struct device *dev) { - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) + if (CONFIG(LINEAR_FRAMEBUFFER)) bochs_init_linear_fb(dev); - else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER)) + else if (CONFIG(VGA_TEXT_FRAMEBUFFER)) bochs_init_text_mode(dev); } diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index ede0232a9a..d647c0cab1 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -338,9 +338,9 @@ static void cirrus_init_text_mode(struct device *dev) static void cirrus_init(struct device *dev) { - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) + if (CONFIG(LINEAR_FRAMEBUFFER)) cirrus_init_linear_fb(dev); - else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER)) + else if (CONFIG(VGA_TEXT_FRAMEBUFFER)) cirrus_init_text_mode(dev); } diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index a8a4128573..6e0d5f7fb8 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -22,7 +22,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #define ADAU7002_ACPI_NAME "ADAU" #define ADAU7002_ACPI_HID "ADAU7002" @@ -71,7 +71,7 @@ static struct device_operations adau7002_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = adau7002_acpi_name, .acpi_fill_ssdt_generator = adau7002_fill_ssdt, #endif diff --git a/src/drivers/generic/generic/chip.h b/src/drivers/generic/generic/chip.h index f3c54b687b..fc470cec0d 100644 --- a/src/drivers/generic/generic/chip.h +++ b/src/drivers/generic/generic/chip.h @@ -16,7 +16,7 @@ #ifndef __GENERIC_GENERIC_CHIP_H__ #define __GENERIC_GENERIC_CHIP_H__ -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpi_device.h> diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 8e5ea0c91e..3c677109b0 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -23,7 +23,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #define MAX98357A_ACPI_NAME "MAXM" #define MAX98357A_ACPI_HID "MX98357A" @@ -76,7 +76,7 @@ static struct device_operations max98357a_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = max98357a_acpi_name, .acpi_fill_ssdt_generator = max98357a_fill_ssdt, #endif diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index ebc22e0d61..5399f75395 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -24,7 +24,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #define DA7219_ACPI_NAME "DLG7" #define DA7219_ACPI_HID "DLGS7219" @@ -113,7 +113,7 @@ static struct device_operations da7219_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = da7219_acpi_name, .acpi_fill_ssdt_generator = da7219_fill_ssdt, #endif diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 617e663472..93b662a63d 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -377,7 +377,7 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, /* Process each segment */ while (count--) { - if (IS_ENABLED(CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG)) { + if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) { printk(BIOS_DEBUG, "i2c %u:%02x %s %d bytes : ", bus, segments->slave, (segments->flags & I2C_M_RD) ? "R" : "W", @@ -401,7 +401,7 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, } } - if (IS_ENABLED(CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG)) { + if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) { int j; for (j = 0; j < segments->len; j++) printk(BIOS_DEBUG, "%02x ", segments->buf[j]); diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 17304a18dc..d78000793e 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -20,7 +20,7 @@ #include <device/i2c.h> #include <stdint.h> -#if IS_ENABLED(CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG) +#if CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG) #define DW_I2C_DEBUG BIOS_DEBUG #else diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index ca2dfafdc5..598f211ed8 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -24,7 +24,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) { @@ -192,7 +192,7 @@ static struct device_operations i2c_generic_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_generic_acpi_name, .acpi_fill_ssdt_generator = i2c_generic_fill_ssdt_generator, #endif diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 952e3e49f0..d570892c1d 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -19,7 +19,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void i2c_hid_fill_dsm(struct device *dev) { struct drivers_i2c_hid_config *config = dev->chip_info; @@ -50,7 +50,7 @@ static struct device_operations i2c_hid_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_hid_acpi_name, .acpi_fill_ssdt_generator = i2c_hid_fill_ssdt_generator, #endif diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 3f905125c4..a98054abd0 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -24,7 +24,7 @@ #include <string.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #define NAU8825_ACPI_NAME "NAU8" #define NAU8825_ACPI_HID "10508825" @@ -102,7 +102,7 @@ static struct device_operations nau8825_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = nau8825_acpi_name, .acpi_fill_ssdt_generator = nau8825_fill_ssdt, #endif diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 1893d167d2..92c89211df 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -143,7 +143,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, ASSERT(sbuf_size >= 10); /* Display the TPM command */ - if (IS_ENABLED(CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES)) { + if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) { printk(BIOS_DEBUG, "TPM Command: 0x%08x\n", read_at_be32(sendbuf, sizeof(uint16_t) + sizeof(uint32_t))); @@ -165,7 +165,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, *rbuf_len = len; /* Display the TPM response */ - if (IS_ENABLED(CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES)) { + if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) { printk(BIOS_DEBUG, "TPM Response: 0x%08x\n", read_at_be32(recvbuf, sizeof(uint16_t) + sizeof(uint32_t))); diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 0c1d86d33d..4b2f55441d 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -61,7 +61,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, struct stopwatch sw; ASSERT(sbuf_size >= 10); - if (IS_ENABLED(CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES)) { + if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) { /* Display the TPM command */ if (sbuf_size >= 10) printk(BIOS_DEBUG, "TPM Command: 0x%08x\n", @@ -106,7 +106,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, /* Determine if there is additional response data */ if (recv_bytes > hdr_bytes) { /* Display the TPM response */ - if (IS_ENABLED(CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES)) + if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) hexdump(recvbuf, hdr_bytes); /* Read the full TPM response */ @@ -120,7 +120,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, *rbuf_len = status; /* Display the TPM response */ - if (IS_ENABLED(CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES)) { + if (CONFIG(DRIVER_TPM_DISPLAY_TIS_BYTES)) { printk(BIOS_DEBUG, "TPM Response: 0x%08x\n", read_at_be32(recvbuf, sizeof(uint16_t) + sizeof(uint32_t))); diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 02b7c375a6..68696362ef 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -142,14 +142,14 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) uint8_t val; uint16_t limit_value; -#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) +#if CONFIG(SMBUS_HAS_AUX_CHANNELS) uint8_t smbus_aux_channel_prev = smbus_get_current_channel(); smbus_switch_to_channel(config->smbus_aux); printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", config->smbus_aux); #endif if (smbus_read_byte(dev, 0x00) < 0) { -#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) +#if CONFIG(SMBUS_HAS_AUX_CHANNELS) /* Restore SMBUS channel setting */ smbus_switch_to_channel(smbus_aux_channel_prev); printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", smbus_aux_channel_prev); @@ -346,7 +346,7 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) val |= W83795_REG_CONFIG_START; w83795_write(dev, W83795_REG_CONFIG, val); -#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) +#if CONFIG(SMBUS_HAS_AUX_CHANNELS) /* Restore SMBUS channel setting */ smbus_switch_to_channel(smbus_aux_channel_prev); printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", smbus_aux_channel_prev); diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 8ac3595867..7897dd4003 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -95,7 +95,7 @@ before_romstage: jmp .Lhlt .Lhlt: -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #endif hlt diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 76241c8f90..088c292e8d 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -57,7 +57,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size; - if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) { + if (CONFIG(MRC_CACHE_FMAP)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { *mrc_region_ptr = rdev_mmap_full(&rdev); diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f64161cc..2da07d519b 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -72,19 +72,19 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) FSP_FSP_INIT FspInitApi; FSP_INIT_PARAMS FspInitParams; FSP_INIT_RT_BUFFER FspRtBuffer; -#if IS_ENABLED(CONFIG_FSP_USES_UPD) +#if CONFIG(FSP_USES_UPD) UPD_DATA_REGION fsp_upd_data; #endif /* Load microcode before RAM init */ - if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; FspInitParams.NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_FSP_USES_UPD) +#if CONFIG(FSP_USES_UPD) FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data; #endif FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer; @@ -238,7 +238,7 @@ void print_fsp_info(void) { } -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ @@ -308,7 +308,7 @@ static void find_fsp_hob_update_mrc(void *unused) /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); - #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) + #if CONFIG(ENABLE_MRC_CACHE) if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index d5d0160e49..f781329d21 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -19,7 +19,7 @@ #include <chipset_fsp_util.h> #include "fsp_values.h" -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) int save_mrc_data(void *hob_start); void *find_and_set_fastboot_cache(void); #endif @@ -61,7 +61,7 @@ void printguid(EFI_GUID *guid); #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cdc8e9381f..3f2a7ae02f 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -30,7 +30,7 @@ /* Switch to the stack in RAM */ movl %eax, %esp -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) +#if CONFIG(SKIP_FSP_CAR) /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car @@ -87,7 +87,7 @@ * +0: Number of variable MTRRs to clear */ -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) push %esp call soc_set_mtrrs @@ -147,7 +147,7 @@ post_code(0x3a) -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) call soc_enable_mtrrs #else /* Enable MTRR. */ diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 70e1ad716f..48fcb8f39f 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -189,7 +189,7 @@ halt2: .Lhlt: xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2c5e9a769e..2702b5a6eb 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -102,7 +102,7 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) (u8)((fsp_header->ImageRevision >> 16) & 0xff), (u8)((fsp_header->ImageRevision >> 8) & 0xff), (u8)(fsp_header->ImageRevision & 0xff)); -#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS) +#if CONFIG(DISPLAY_FSP_ENTRY_POINTS) printk(BIOS_SPEW, "FSP Entry Points:\n"); printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base); printk(BIOS_SPEW, " 0x%p: TempRamInit\n", diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7fed2a1789..2dd5c77e96 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -51,7 +51,7 @@ void raminit(struct romstage_params *params) VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif @@ -101,13 +101,13 @@ void raminit(struct romstage_params *params) soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); - if (IS_ENABLED(CONFIG_MMA)) + if (CONFIG(MMA)) setup_mma(&memory_init_params); post_code(POST_MEM_PREINIT_PREP_END); /* Display the UPD data */ - if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + if (CONFIG(DISPLAY_UPD_DATA)) soc_display_memory_init_params(original_params, &memory_init_params); @@ -146,7 +146,7 @@ void raminit(struct romstage_params *params) } /* Display SMM area */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) char *smm_base; size_t smm_size; @@ -162,7 +162,7 @@ void raminit(struct romstage_params *params) fsp_reserved_bytes); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ @@ -194,7 +194,7 @@ void raminit(struct romstage_params *params) memory_info_hob); } -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) if (hob_list_ptr == NULL) die("ERROR - HOB pointer is NULL!\n"); @@ -266,7 +266,7 @@ void raminit(struct romstage_params *params) (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) if (cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab4509f..814bddf007 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -55,7 +55,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) int missing_hob = 0; void *hob_list_ptr = get_hob_list(); - if (!IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (!CONFIG(DISPLAY_HOBS)) return; /* Verify the HOBs */ @@ -117,12 +117,12 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) soc_silicon_init_params(&silicon_init_params); /* Locate VBT and pass to FSP GOP */ - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); /* Display the UPD data */ - if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + if (CONFIG(DISPLAY_UPD_DATA)) soc_display_silicon_init_params(original_params, &silicon_init_params); @@ -139,7 +139,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); /* Mark graphics init done after SiliconInit if VBT was provided */ -#if IS_ENABLED(CONFIG_RUN_FSP_GOP) +#if CONFIG(RUN_FSP_GOP) /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs * to be #if'd out instead of using if (). */ if (silicon_init_params.GraphicsConfigPtr) @@ -152,10 +152,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) static void fsp_cache_save(struct prog *fsp) { - if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) + if (CONFIG(DISPLAY_SMM_MEMORY_MAP)) smm_memory_map(); - if (IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (CONFIG(NO_STAGE_CACHE)) return; printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); @@ -192,7 +192,7 @@ void fsp_load(void) if (load_done) return; - if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); } else { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 31d696ff56..ebb6a6678b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -52,13 +52,13 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) timestamp_add_now(TS_START_ROMSTAGE); /* Load microcode before RAM init */ - if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); memset(&pei_data, 0, sizeof(pei_data)); /* Display parameters */ - if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); @@ -104,7 +104,7 @@ void romstage_common(struct romstage_params *params) pei_data->boot_mode = params->power_state->prev_sleep_state; s3wake = params->power_state->prev_sleep_state == ACPI_S3; - if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) + if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); /* Perform remaining SOC initialization */ @@ -119,7 +119,7 @@ void romstage_common(struct romstage_params *params) /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) + } else if (CONFIG(CACHE_MRC_SETTINGS) && (!mrc_cache_get_current(MRC_TRAINING_DATA, params->fsp_version, &rdev))) { @@ -128,7 +128,7 @@ void romstage_common(struct romstage_params *params) region_device_sz(&rdev); params->pei_data->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (params->pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, @@ -146,7 +146,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); /* Save MRC output */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + if (CONFIG(CACHE_MRC_SETTINGS)) { printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, pei_data->data_to_save_size); if ((params->pei_data->boot_mode != ACPI_S3) @@ -214,7 +214,7 @@ __weak void mainboard_save_dimm_info( memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) { + if (CONFIG(DISPLAY_HOBS)) { printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); printk(BIOS_DEBUG, " 0x%02x: Revision\n", memory_info_hob->Revision); diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index eb2a6371a8..88ff36a847 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -116,7 +116,7 @@ void *setup_stack_and_mtrrs(void) slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); num_mtrrs++; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uint32_t tseg_base; diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 90012ffb32..51d0f59324 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -34,7 +34,7 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) /* Get VBT data */ vbt_data = locate_vbt(&vbt_len); if (vbt_data != NULL) { - if (IS_ENABLED(CONFIG_DISPLAY_VBT)) { + if (CONFIG(DISPLAY_VBT)) { /* Display the vbt file contents */ printk(BIOS_DEBUG, "VBT Data:\n"); hexdump(vbt_data, vbt_len); diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index d098772004..a2a9345474 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -31,11 +31,11 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, display_mtrrs(); /* Display the UPD values */ - if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + if (CONFIG(DISPLAY_UPD_DATA)) fspm_display_upd_values(fspm_old_upd, fspm_new_upd); /* Display the call entry point and parameters */ - if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init); printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd); @@ -44,7 +44,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, void fsp_debug_after_memory_init(uint32_t status) { - if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspMemoryInit returned 0x%08x\n", status); if (status != FSP_SUCCESS) @@ -55,9 +55,9 @@ void fsp_debug_after_memory_init(uint32_t status) die("ERROR - HOB list pointer was not returned!\n"); /* Display and verify the HOBs */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (CONFIG(DISPLAY_HOBS)) fsp_display_hobs(); - if (IS_ENABLED(CONFIG_VERIFY_HOBS)) + if (CONFIG(VERIFY_HOBS)) fsp_verify_memory_init_hobs(); display_mtrrs(); @@ -74,11 +74,11 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, display_mtrrs(); /* Display the UPD values */ - if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + if (CONFIG(DISPLAY_UPD_DATA)) soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd); /* Display the call to FSP SiliconInit */ - if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); @@ -86,11 +86,11 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, void fsp_debug_after_silicon_init(uint32_t status) { - if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); /* Display the HOBs */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (CONFIG(DISPLAY_HOBS)) fsp_display_hobs(); display_mtrrs(); @@ -104,7 +104,7 @@ void fsp_before_debug_notify(fsp_notify_fn notify, const struct fsp_notify_params *notify_params) { /* Display the call to FspNotify */ - if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; printk(BIOS_SPEW, "0x%08x: notify_params->phase\n", notify_params->phase); @@ -114,11 +114,11 @@ void fsp_before_debug_notify(fsp_notify_fn notify, void fsp_debug_after_notify(uint32_t status) { - if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); /* Display the HOBs */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (CONFIG(DISPLAY_HOBS)) fsp_display_hobs(); display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 86f0b266fe..5efd59058c 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -219,7 +219,7 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) static void display_fsp_version_info_hob(const void *hob, size_t size) { -#if IS_ENABLED(CONFIG_DISPLAY_FSP_VERSION_INFO) +#if CONFIG(DISPLAY_FSP_VERSION_INFO) const FIRMWARE_VERSION_INFO *fvi; const FIRMWARE_VERSION_INFO_HOB *fvih = (FIRMWARE_VERSION_INFO_HOB *)hob; diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 7d3a10210e..c7fad95aed 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -26,7 +26,7 @@ #include <Base.h> #include <FspmUpd.h> #include <FspsUpd.h> -#if IS_ENABLED(CONFIG_DISPLAY_FSP_VERSION_INFO) +#if CONFIG(DISPLAY_FSP_VERSION_INFO) #include <FirmwareVersionInfoHob.h> #endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 2002c1194e..3dafcf8ad9 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -38,7 +38,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) size_t mrc_data_size; const void *mrc_data; - if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) || s3wake) + if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake) return; mrc_data = fsp_find_nv_storage_data(&mrc_data_size); @@ -57,7 +57,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) + if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) mrc_cache_update_hash(mrc_data, mrc_data_size); } @@ -74,7 +74,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) range_entry_size(&fsp_mem)); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + if (CONFIG(HAVE_ACPI_RESUME)) { printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ @@ -97,8 +97,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) * Initialize the TPM, unless the TPM was already initialized * in verstage and used to verify romstage. */ - if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && - !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + if ((CONFIG(TPM1) || CONFIG(TPM2)) && + !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) tpm_setup(s3wake); } @@ -109,7 +109,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) arch_upd->NvsBufferPtr = NULL; - if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (!CONFIG(CACHE_MRC_SETTINGS)) return; /* @@ -118,7 +118,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) * 2. Memory retrain switch is set. */ if (vboot_recovery_mode_enabled()) { - if (!IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) return; if (vboot_recovery_mode_memory_retrain()) return; @@ -128,13 +128,13 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) return; /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); data = rdev_mmap_full(&rdev); if (data == NULL) return; - if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH) && + if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && !mrc_cache_verify_hash(data, region_device_sz(&rdev))) return; @@ -174,7 +174,7 @@ static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, * setting up seprate stack frame. FSP 2.1 would not relocate stack * top and does not reinitialize stack pointer. */ - if (IS_ENABLED(CONFIG_FSP_USES_CB_STACK)) { + if (CONFIG(FSP_USES_CB_STACK)) { arch_upd->StackBase = (void *)_car_stack_end; arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE; return CB_SUCCESS; @@ -254,7 +254,7 @@ static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) /* Use the full FSP version by default. */ uint32_t ver = hdr->fsp_revision; - if (!IS_ENABLED(CONFIG_FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) + if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) return ver; ver &= ~0xff; @@ -298,7 +298,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); - if (IS_ENABLED(CONFIG_MMA)) + if (CONFIG(MMA)) setup_mma(&fspm_upd.FspmConfig); post_code(POST_MEM_PREINIT_PREP_END); @@ -383,7 +383,7 @@ void fsp_memory_init(bool s3wake) struct memranges memmap; struct range_entry freeranges[2]; - if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) + if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); if (cbfs_boot_locate(&file_desc, name, NULL)) { @@ -399,7 +399,7 @@ void fsp_memory_init(bool s3wake) _car_relocatable_data_end - _car_region_start, 0); memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); - if (!IS_ENABLED(CONFIG_FSP_M_XIP)) + if (!CONFIG(FSP_M_XIP)) status = load_fspm_mem(&hdr, &file_data, &memmap); else status = load_fspm_xip(&hdr, &file_data); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 06706639ce..402b05d55e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -77,7 +77,7 @@ void fsps_load(bool s3wake) if (load_done) return; - if (s3wake && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (s3wake && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsps); if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 5aaa17fe94..19b8127ac5 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -80,7 +80,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, rdev_munmap(rdev, membase); - if (IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER)) + if (CONFIG(DISPLAY_FSP_HEADER)) fsp_print_header_info(hdr); /* Check if size specified in the header matches the cbfs file size */ diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index 4a445e55db..176ae24bf1 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -26,7 +26,7 @@ enum { }; -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type); #else diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 0c51c7000a..2e200ff828 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -91,7 +91,7 @@ void intel_gma_opregion_register(uintptr_t opregion) * Atom-based platforms use a combined SMI/SCI register, * whereas non-Atom platforms use a separate SCI register. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) + if (CONFIG(INTEL_GMA_SWSMISCI)) sci_reg = SWSMISCI; else sci_reg = SWSCI; diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 91accdf5b7..7455704530 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -60,7 +60,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf, genfeat->flexaim = 1; genfeat->download_ext_vbt = 1; genfeat->enable_ssc = conf->use_spread_spectrum_clock; - genfeat->ssc_freq = IS_ENABLED(CONFIG_INTEL_GMA_SSC_ALTERNATE_REF); + genfeat->ssc_freq = CONFIG(INTEL_GMA_SSC_ALTERNATE_REF); genfeat->rsvd10 = 0x4; genfeat->legacy_monitor_detect = 1; genfeat->int_crt_support = 1; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index bb617d5d0a..d78b0076fa 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -32,7 +32,7 @@ #define PMCS_DR 0xcc #define PME_STS (1 << 15) -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) { @@ -71,7 +71,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) return -1; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void emit_sar_acpi_structures(void) { int i, j, package_size; @@ -139,7 +139,7 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); - if (!IS_ENABLED(CONFIG_GEO_SAR_ENABLE)) + if (!CONFIG(GEO_SAR_ENABLE)) return; /* @@ -219,7 +219,7 @@ static void intel_wifi_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); /* Fill regulatory domain structure */ - if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) { + if (CONFIG(HAVE_REGULATORY_DOMAIN)) { /* * Name ("WRDD", Package () { * WRDD_REVISION, // Revision @@ -240,7 +240,7 @@ static void intel_wifi_fill_ssdt(struct device *dev) } /* Fill Wifi sar related ACPI structures */ - if (IS_ENABLED(CONFIG_USE_SAR)) + if (CONFIG(USE_SAR)) emit_sar_acpi_structures(); acpigen_pop_len(); /* Device */ @@ -260,7 +260,7 @@ static void wifi_pci_dev_init(struct device *dev) { pci_dev_init(dev); - if (IS_ENABLED(CONFIG_ELOG)) { + if (CONFIG(ELOG)) { uint32_t val; val = pci_read_config16(dev, PMCS_DR); if (val & PME_STS) @@ -277,11 +277,11 @@ struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = wifi_pci_dev_init, -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = smbios_write_wifi, #endif .ops_pci = &pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = intel_wifi_acpi_name, .acpi_fill_ssdt_generator = intel_wifi_fill_ssdt, #endif diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index ca807efe63..9dcbf15d93 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -49,12 +49,12 @@ drivers_lenovo_is_wacom_present(void) if (result != -1) return result; - if (IS_ENABLED(CONFIG_DIGITIZER_PRESENT)) { + if (CONFIG(DIGITIZER_PRESENT)) { printk (BIOS_INFO, "Digitizer state forced as present\n"); return (result = 1); } - if (IS_ENABLED(CONFIG_DIGITIZER_ABSENT)) { + if (CONFIG(DIGITIZER_ABSENT)) { printk (BIOS_INFO, "Digitizer state forced as absent\n"); return (result = 0); } diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 84bbdb05b3..582c5c64cf 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -65,7 +65,7 @@ static const struct cache_region recovery_training = { .cbmem_id = CBMEM_ID_MRCDATA, .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, -#if IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE) +#if CONFIG(HAS_RECOVERY_MRC_CACHE) .flags = RECOVERY_FLAG, #else .flags = 0, @@ -431,10 +431,10 @@ static int nvm_is_write_protected(void) u8 wp_gpio; u8 wp_spi; - if (!IS_ENABLED(CONFIG_CHROMEOS)) + if (!CONFIG(CHROMEOS)) return 0; - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; /* Read Write Protect GPIO if available */ @@ -458,10 +458,10 @@ static int nvm_protect(const struct region *r) { const struct spi_flash *flash = boot_device_spi_flash(); - if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)) + if (!CONFIG(MRC_SETTINGS_PROTECT)) return 0; - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; return spi_flash_ctrlr_protect_region(flash, r, WRITE_PROTECT); @@ -472,7 +472,7 @@ static int protect_mrc_cache(const char *name) { struct region region; - if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)) + if (!CONFIG(MRC_SETTINGS_PROTECT)) return 0; if (lookup_region_by_name(name, ®ion) < 0) { @@ -507,7 +507,7 @@ static void protect_mrc_region(void) if (protect_mrc_cache(UNIFIED_MRC_CACHE) == 0) return; - if (IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + if (CONFIG(HAS_RECOVERY_MRC_CACHE)) protect_mrc_cache(RECOVERY_MRC_CACHE); protect_mrc_cache(DEFAULT_MRC_CACHE); @@ -548,10 +548,10 @@ static void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); - if (IS_ENABLED(CONFIG_MRC_SETTINGS_VARIABLE_DATA)) + if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) update_mrc_cache_by_type(MRC_VARIABLE_DATA); - if (IS_ENABLED(CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) + if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) invalidate_normal_cache(); protect_mrc_region(); @@ -562,7 +562,7 @@ static void update_mrc_cache(void *unused) * Some implementations may require this to be later than others. */ -#if IS_ENABLED(CONFIG_MRC_WRITE_NV_LATE) +#if CONFIG(MRC_WRITE_NV_LATE) BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); #else BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 4057ffde52..3200163ab3 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -190,7 +190,7 @@ static void program_mac_address(struct device *dev, u16 io_base) bool mac_found = false; /* check the VPD for the mac address */ - if (IS_ENABLED(CONFIG_RT8168_GET_MAC_FROM_VPD)) { + if (CONFIG(RT8168_GET_MAC_FROM_VPD)) { /* Current implementation is up to 10 NIC cards */ if (config && config->device_index <= MAX_DEVICE_SUPPORT) { /* check "ethernet_mac" first when the device index is 1 */ @@ -294,11 +294,11 @@ static void r8168_init(struct device *dev) program_mac_address(dev, io_base); /* Program customized LED mode */ - if (IS_ENABLED(CONFIG_RT8168_SET_LED_MODE)) + if (CONFIG(RT8168_SET_LED_MODE)) r8168_set_customized_led(dev, io_base); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #define R8168_ACPI_HID "R8168" static void r8168_net_fill_ssdt(struct device *dev) { @@ -346,7 +346,7 @@ static struct device_operations r8168_ops = { .enable_resources = pci_dev_enable_resources, .init = r8168_init, .scan_bus = 0, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = r8168_net_acpi_name, .acpi_fill_ssdt_generator = r8168_net_fill_ssdt, #endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 27c7bfdbe1..4b81d58e46 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -31,7 +31,7 @@ void setup_i8254(void) outb(0x12, TIMER1_PORT); } -#if IS_ENABLED(CONFIG_UDELAY_TIMER2) +#if CONFIG(UDELAY_TIMER2) static void load_timer2(unsigned int ticks) { /* Set up the timer gate, turn off the speaker */ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3b22a46298..c18f1e947b 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -30,7 +30,7 @@ #include <security/vboot/vbnv_layout.h> /* There's no way around this include guard. option_table.h is autogenerated */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include "option_table.h" #else #define LB_CKS_RANGE_START 0 @@ -41,7 +41,7 @@ #include <smp/spinlock.h> #if (defined(__PRE_RAM__) && \ -IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)) +CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)) #define LOCK_NVRAM_CBFS_SPINLOCK() spin_lock(romstage_nvram_cbfs_lock()) #define UNLOCK_NVRAM_CBFS_SPINLOCK() spin_unlock(romstage_nvram_cbfs_lock()) #else @@ -70,7 +70,7 @@ static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) int i; u16 sum, old_sum; - if (IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) + if (CONFIG(STATIC_OPTION_TABLE)) return 1; sum = 0; @@ -122,7 +122,7 @@ static bool __cmos_init(bool invalid) x = cmos_read(RTC_VALID); cmos_invalid = !(x & RTC_VRT); - if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + if (CONFIG(USE_OPTION_TABLE)) { /* See if there is a CMOS checksum error */ checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); @@ -162,7 +162,7 @@ static bool __cmos_init(bool invalid) /* Ensure all reserved bits are 0 in register D */ cmos_write(RTC_VRT, RTC_VALID); - if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + if (CONFIG(USE_OPTION_TABLE)) { /* See if there is a LB CMOS checksum error */ checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); @@ -196,7 +196,7 @@ static void cmos_init_vbnv(bool invalid) void cmos_init(bool invalid) { - if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + if (CONFIG(VBOOT_VBNV_CMOS)) cmos_init_vbnv(invalid); else __cmos_init(invalid); @@ -272,7 +272,7 @@ enum cb_err get_option(void *dest, const char *name) size_t namelen; int found = 0; - if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + if (!CONFIG(USE_OPTION_TABLE)) return CB_CMOS_OTABLE_DISABLED; LOCK_NVRAM_CBFS_SPINLOCK(); @@ -370,7 +370,7 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, { printk(BIOS_NOTICE, "NOTICE: read_option() used to access CMOS " "from non-ROMCC code, please use get_option() instead.\n"); - if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + if (CONFIG(USE_OPTION_TABLE)) { const unsigned char byte = cmos_read(start / 8); return (byte >> (start & 7U)) & ((1U << size) - 1U); } @@ -386,7 +386,7 @@ enum cb_err set_option(const char *name, void *value) size_t namelen; int found = 0; - if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + if (!CONFIG(USE_OPTION_TABLE)) return CB_CMOS_OTABLE_DISABLED; /* Figure out how long name is */ @@ -506,7 +506,7 @@ void set_boot_successful(void) byte = inb(RTC_PORT(1)); - if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { + if (CONFIG(SKIP_MAX_REBOOT_CNT_CLEAR)) { /* * Set the fallback boot bit to allow for recovery if * the payload fails to boot. diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index c5cd86ce85..26bcac5acf 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -18,7 +18,7 @@ #include <cbfs.h> #endif #include <pc80/mc146818rtc.h> -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include <option_table.h> #endif @@ -34,7 +34,7 @@ int cmos_error(void) int cmos_chksum_valid(void); int cmos_chksum_valid(void) { -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) unsigned char addr; u16 sum, old_sum; @@ -53,11 +53,11 @@ int cmos_chksum_valid(void) #endif } -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) void sanitize_cmos(void) { if (cmos_error() || !cmos_chksum_valid() || - IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { + CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = #ifdef __ROMCC__ diff --git a/src/drivers/pc80/rtc/mc146818rtc_romcc.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c index a280882a77..eb8bf0022a 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_romcc.c +++ b/src/drivers/pc80/rtc/mc146818rtc_romcc.c @@ -63,7 +63,7 @@ static inline __attribute__((unused)) int do_normal_boot(void) unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) { -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) unsigned byte; byte = cmos_read(start/8); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index d7925bcea5..e10332ba0a 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -45,7 +45,7 @@ #define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ - if (IS_ENABLED(CONFIG_DEBUG_TPM)) { \ + if (CONFIG(DEBUG_TPM)) { \ printk(BIOS_DEBUG, PREFIX); \ printk(BIOS_DEBUG, fmt, ##args); \ } @@ -126,7 +126,7 @@ static const struct device_name atmel_devices[] = { static const struct device_name infineon_devices[] = { {0x000b, "SLB9635 TT 1.2"}, -#if IS_ENABLED(CONFIG_TPM2) +#if CONFIG(TPM2) {0x001a, "SLB9665 TT 2.0"}, {0x001b, "SLB9670 TT 2.0"}, #else @@ -602,7 +602,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) * and tis_has_valid_data(), or some race-condition-related * issue will occur. */ - if (IS_ENABLED(CONFIG_TPM_RDRESP_NEED_DELAY)) + if (CONFIG(TPM_RDRESP_NEED_DELAY)) udelay(10); } while (tis_has_valid_data(locality)); @@ -783,7 +783,7 @@ static void lpc_tpm_set_resources(struct device *dev) } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void tpm_ppi_func0_cb(void *arg) { @@ -794,7 +794,7 @@ static void tpm_ppi_func0_cb(void *arg) static void tpm_ppi_func1_cb(void *arg) { - if (IS_ENABLED(CONFIG_TPM2)) + if (CONFIG(TPM2)) /* Interface version: 2.0 */ acpigen_write_return_string("2.0"); else @@ -942,7 +942,7 @@ static void lpc_tpm_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_footer(); - if (!IS_ENABLED(CONFIG_CHROMEOS)) { + if (!CONFIG(CHROMEOS)) { /* * _DSM method */ @@ -981,7 +981,7 @@ static const char *lpc_tpm_acpi_name(const struct device *dev) static struct device_operations lpc_tpm_ops = { .read_resources = lpc_tpm_read_resources, .set_resources = lpc_tpm_set_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_tpm_acpi_name, .acpi_fill_ssdt_generator = lpc_tpm_fill_ssdt, #endif diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 01b4f53adf..831ac7954f 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -140,7 +140,7 @@ static void nc_fpga_init(struct device *dev) } } -#if IS_ENABLED(CONFIG_NC_FPGA_NOTIFY_CB_READY) +#if CONFIG(NC_FPGA_NOTIFY_CB_READY) /* Set FW_DONE bit in FPGA before jumping to payload. */ static void set_fw_done(void *unused) { diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a8d1..489b82ff46 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -58,7 +58,7 @@ static int lookup_store(struct region_device *rstore) { struct cbfsf file; - if (IS_ENABLED(CONFIG_SMMSTORE_IN_CBFS)) { + if (CONFIG(SMMSTORE_IN_CBFS)) { if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 5195bec6b7..a805609c5e 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -162,7 +162,7 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -188,7 +188,7 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif @@ -201,7 +201,7 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = adesto_write, .erase = spi_flash_cmd_erase, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index b0e926e898..64c91cc79f 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -136,7 +136,7 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -163,7 +163,7 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, byte_addr = 0; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: AMIC: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif @@ -176,7 +176,7 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = amic_write, .erase = spi_flash_cmd_erase, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index d81e0e3729..7d6e172755 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -118,7 +118,7 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -144,7 +144,7 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Atmel: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif @@ -157,7 +157,7 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = atmel_write, .erase = spi_flash_cmd_erase, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index fa155138fd..33e12a000f 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -257,7 +257,7 @@ static int eon_write(const struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -279,7 +279,7 @@ static int eon_write(const struct spi_flash *flash, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ %#x\n", len, (unsigned int)(offset - len)); #endif diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index ff1ce2f8e6..83216c06d1 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -184,7 +184,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, @@ -206,7 +206,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n", len, (unsigned int)(offset - len)); @@ -222,7 +222,7 @@ static const struct spi_flash_ops spi_flash_ops = { .write = gigadevice_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index d9f0044380..1610ca18c8 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -230,7 +230,7 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -256,7 +256,7 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Macronix: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif @@ -268,7 +268,7 @@ static const struct spi_flash_ops spi_flash_ops = { .write = macronix_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 2e924343e6..e687bf8471 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -245,7 +245,7 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -271,7 +271,7 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n", len, offset); #endif diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1f52271eb..71dc660d2b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -217,7 +217,7 @@ int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) spi_flash_addr(offset, cmd); offset += erase_size; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); #endif @@ -276,38 +276,38 @@ static struct { struct spi_flash *flash); } flashes[] = { /* Keep it sorted by define name */ -#if IS_ENABLED(CONFIG_SPI_FLASH_AMIC) +#if CONFIG(SPI_FLASH_AMIC) { 0, 0x37, spi_flash_probe_amic, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_ATMEL) +#if CONFIG(SPI_FLASH_ATMEL) { 0, 0x1f, spi_flash_probe_atmel, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_EON) +#if CONFIG(SPI_FLASH_EON) { 0, 0x1c, spi_flash_probe_eon, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_GIGADEVICE) +#if CONFIG(SPI_FLASH_GIGADEVICE) { 0, 0xc8, spi_flash_probe_gigadevice, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_MACRONIX) +#if CONFIG(SPI_FLASH_MACRONIX) { 0, 0xc2, spi_flash_probe_macronix, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_SPANSION) +#if CONFIG(SPI_FLASH_SPANSION) { 0, 0x01, spi_flash_probe_spansion, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_SST) +#if CONFIG(SPI_FLASH_SST) { 0, 0xbf, spi_flash_probe_sst, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_STMICRO) +#if CONFIG(SPI_FLASH_STMICRO) { 0, 0x20, spi_flash_probe_stmicro, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_WINBOND) +#if CONFIG(SPI_FLASH_WINBOND) { 0, 0xef, spi_flash_probe_winbond, }, #endif /* Keep it sorted by best detection */ -#if IS_ENABLED(CONFIG_SPI_FLASH_STMICRO) +#if CONFIG(SPI_FLASH_STMICRO) { 0, 0xff, spi_flash_probe_stmicro, }, #endif -#if IS_ENABLED(CONFIG_SPI_FLASH_ADESTO) +#if CONFIG(SPI_FLASH_ADESTO) { 0, 0x1f, spi_flash_probe_adesto, }, #endif }; @@ -324,7 +324,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi, if (ret) return -1; - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_SPEW, "SF: Got idcode: "); for (i = 0; i < sizeof(idcode); i++) printk(BIOS_SPEW, "%02x ", idcode[i]); @@ -511,7 +511,7 @@ int spi_flash_volatile_group_begin(const struct spi_flash *flash) uint32_t count; int ret = 0; - if (!IS_ENABLED(CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP)) + if (!CONFIG(SPI_FLASH_HAS_VOLATILE_GROUP)) return ret; count = car_get_var(volatile_group_count); @@ -528,7 +528,7 @@ int spi_flash_volatile_group_end(const struct spi_flash *flash) uint32_t count; int ret = 0; - if (!IS_ENABLED(CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP)) + if (!CONFIG(SPI_FLASH_HAS_VOLATILE_GROUP)) return ret; count = car_get_var(volatile_group_count); @@ -547,7 +547,7 @@ void lb_spi_flash(struct lb_header *header) struct lb_spi_flash *flash; const struct spi_flash *spi_flash_dev; - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return; flash = (struct lb_spi_flash *)lb_new_record(header); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 63fae95636..71bdac72a2 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -168,7 +168,7 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) offset, }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif @@ -223,7 +223,7 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -250,7 +250,7 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, } done: -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", ret ? "failure" : "success", len, (unsigned long)offset - actual); #endif @@ -284,7 +284,7 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, cmd[3] = offset; for (; actual < len - 1; actual += 2) { -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); @@ -313,7 +313,7 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, ret = sst_byte_write(flash, offset, buf + actual); done: -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", ret ? "failure" : "success", len, (unsigned long)offset - actual); #endif diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index a89fc563e3..fb24b27266 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -312,7 +312,7 @@ static int stmicro_write(const struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -338,7 +338,7 @@ static int stmicro_write(const struct spi_flash *flash, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: STMicro: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 8bf8fcd8d3..5a75ccc766 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -300,7 +300,7 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -326,7 +326,7 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, offset += chunk_len; } -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Winbond: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif @@ -657,7 +657,7 @@ static const struct spi_flash_ops spi_flash_ops = { .write = winbond_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if IS_ENABLED(CONFIG_SPI_FLASH_NO_FAST_READ) +#if CONFIG(SPI_FLASH_NO_FAST_READ) .read = spi_flash_cmd_read_slow, #else .read = spi_flash_cmd_read_fast, diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 77d3a8e81e..4d8b0a35a4 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -18,13 +18,13 @@ #include <bootstate.h> #include <security/tpm/tspi.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif static void init_tpm_dev(void *unused) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) int s3resume = acpi_is_wakeup_s3(); tpm_setup(s3resume); #else diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9b5f57cbbd..62671e2b6f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -101,7 +101,7 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) { + if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index cf9acf44a1..c3dff6a72c 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -31,7 +31,7 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) +#if CONFIG(DRIVERS_UART_8250MEM_32) static uint8_t uart8250_read(void *base, uint8_t reg) { return read32(base + 4 * reg) & 0xff; @@ -156,7 +156,7 @@ void uart_fill_lb(void *data) if (!serial.baseaddr) return; serial.baud = get_uart_baudrate(); - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (CONFIG(DRIVERS_UART_8250MEM_32)) serial.regwidth = sizeof(uint32_t); else serial.regwidth = sizeof(uint8_t); diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index e712600f78..2f8aa842b3 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -22,7 +22,7 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, return (1 + (2 * refclk) / (baudrate * oversample)) / 2; } -#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER) +#if !CONFIG(UART_OVERRIDE_INPUT_CLOCK_DIVIDER) unsigned int uart_input_clock_divider(void) { /* Specify the default oversample rate for the UART. @@ -39,7 +39,7 @@ unsigned int uart_input_clock_divider(void) } #endif -#if !IS_ENABLED(CONFIG_UART_OVERRIDE_REFCLK) +#if !CONFIG(UART_OVERRIDE_REFCLK) unsigned int uart_platform_refclk(void) { /* Specify the default input clock frequency for the UART. diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index d867d6c972..638b7c7e58 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -35,7 +35,7 @@ struct ehci_debug_info { struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; } __packed; -#if IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT) +#if CONFIG(DEBUG_CONSOLE_INIT) /* When selected, you can debug the connection of usbdebug dongle. * EHCI port register bits and USB packets are dumped on console, * assuming some other console already works. @@ -217,7 +217,7 @@ static void dbgp_print_data(struct ehci_dbg_port *ehci_debug) int len; u32 ctrl, lo, hi; - if (!IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT) || dbgp_enabled()) + if (!CONFIG(DEBUG_CONSOLE_INIT) || dbgp_enabled()) return; ctrl = read32(&ehci_debug->control); @@ -720,7 +720,7 @@ static void migrate_ehci_debug(int is_recovery) return; } - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) { + if (CONFIG(USBDEBUG_IN_PRE_RAM)) { /* Use state in CBMEM. */ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG); if (dbg_info_cbmem) @@ -759,13 +759,13 @@ void usbdebug_init(void) * CBMEM_INIT_HOOKs for postcar and ramstage as we recover state * from CBMEM. */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM) + if (CONFIG(USBDEBUG_IN_PRE_RAM) && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) usbdebug_hw_init(false); /* USB console init is done early in ramstage if it was * not done in romstage, this does not require CBMEM. */ - if (!IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM) && ENV_RAMSTAGE) + if (!CONFIG(USBDEBUG_IN_PRE_RAM) && ENV_RAMSTAGE) usbdebug_hw_init(false); } diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 3254a8a1c2..61e103160b 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -342,7 +342,7 @@ int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) } } - if (IS_ENABLED(CONFIG_USBDEBUG_DONGLE_FTDI_FT232H)) { + if (CONFIG(USBDEBUG_DONGLE_FTDI_FT232H)) { ret = probe_for_ftdi(ehci_debug, pipe); } else { ret = probe_for_debug_descriptor(ehci_debug, pipe); diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index e0524dde08..0d25e254e2 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -853,7 +853,7 @@ static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info, pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) + if (CONFIG(LINEAR_FRAMEBUFFER)) XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); data = xgifb_reg_get(pVBInfo->P3c4, 0x21); diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index ee7a7a8f7a..795b8a5fe0 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -118,7 +118,7 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->video_size = video_size_max; } - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ xgifb_reg_or(XGISR, IND_SIS_PCI_ADDRESS_SET, @@ -263,7 +263,7 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->mode_idx = XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info); else - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) + if (CONFIG(LINEAR_FRAMEBUFFER)) xgifb_info->mode_idx = DEFAULT_MODE; else xgifb_info->mode_idx = DEFAULT_TEXT_MODE; @@ -338,7 +338,7 @@ int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) hw_info = &xgifb_info->hw_info; - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { /* Set mode */ XGIfb_pre_setmode(xgifb_info); if (XGISetModeNew(xgifb_info, hw_info, diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 72c5d7c637..3544b8d69e 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -39,7 +39,7 @@ static void xgi_z9s_init(struct device *dev) u8 ret; struct xgifb_video_info *xgifb_info; - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { printk(BIOS_INFO, "XGI Z9s: initializing video device\n"); xgifb_info = malloc(sizeof(*xgifb_info)); ret = xgifb_probe(dev, xgifb_info); diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index b2e65d0e31..962988e7a9 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -94,7 +94,7 @@ Device (EC0) USPP, 8, // USB Port Power } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) +#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE) Field (EMEM, ByteAcc, Lock, Preserve) @@ -525,7 +525,7 @@ Device (EC0) } } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) +#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) /* * Enable USB Port Power * Arg0 = USB port ID diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 70b3f493eb..629144c584 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -413,7 +413,7 @@ static void google_chromeec_log_device_events(uint64_t mask) uint64_t events; int i; - if (!IS_ENABLED(CONFIG_ELOG) || !mask) + if (!CONFIG(ELOG) || !mask) return; if (google_chromeec_check_feature(EC_FEATURE_DEVICE_EVENT) != 1) @@ -434,7 +434,7 @@ void google_chromeec_log_events(uint64_t mask) uint64_t wake_mask; bool restore_wake_mask = false; - if (!IS_ENABLED(CONFIG_ELOG)) + if (!CONFIG(ELOG)) return; /* @@ -536,7 +536,7 @@ int google_chromeec_set_sku_id(u32 skuid) return 0; } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_RTC) +#if CONFIG(EC_GOOGLE_CHROMEEC_RTC) int rtc_get(struct rtc_time *time) { struct chromeec_command cmd; diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 7770d602e3..2eecced721 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -22,7 +22,7 @@ #include "ec.h" #include "ec_commands.h" -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3) +#if CONFIG(EC_GOOGLE_CHROMEEC_I2C_PROTO3) #define PROTO3_FRAMING_BYTES sizeof(uint32_t) /* Just use the LPC host packet size to size the buffer. */ diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 61005d3e3b..7293cffcd3 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -38,7 +38,7 @@ static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum) { int i; -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) +#if CONFIG(EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { u8 ret = mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE, @@ -77,7 +77,7 @@ static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum) { int i; -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) +#if CONFIG(EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { u8 ret = mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE, @@ -132,7 +132,7 @@ static int google_chromeec_wait_ready(u16 port) EC_LPC_CMDR_BUSY, 0); } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) +#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) /* Read memmap data through ACPI port 66/62 */ static int read_memmap(u8 *data, u8 offset) { @@ -166,7 +166,7 @@ static int google_chromeec_command_version(void) { u8 id1, id2, flags; -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) +#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) if (read_memmap(&id1, EC_MEMMAP_ID) || read_memmap(&id2, EC_MEMMAP_ID + 1) || read_memmap(&flags, EC_MEMMAP_HOST_CMD_FLAGS)) { @@ -386,7 +386,7 @@ void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size) uint16_t base; size_t size; - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC_MEC)) { base = MEC_EMI_BASE; size = MEC_EMI_SIZE; } else { diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index cab71928da..eec888ecff 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -26,7 +26,7 @@ static int chromeec_process_one_event(void) uint8_t event = google_chromeec_get_event(); /* Log this event */ - if (IS_ENABLED(CONFIG_ELOG_GSMI) && event) + if (CONFIG(ELOG_GSMI) && event) elog_add_event_byte(ELOG_TYPE_EC_EVENT, event); switch (event) { diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 1cf26a2729..7b3f4d4cf1 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -17,10 +17,10 @@ #include <cbmem.h> #include <ec/google/chromeec/ec.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC) +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC) int get_lid_switch(void) { - if (!IS_ENABLED(CONFIG_VBOOT_LID_SWITCH)) + if (!CONFIG(VBOOT_LID_SWITCH)) return -1; return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); @@ -30,7 +30,7 @@ int get_lid_switch(void) int get_recovery_mode_switch(void) { /* Check for dedicated recovery switch first. */ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC) && + if (CONFIG(EC_GOOGLE_CHROMEEC_LPC) && (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)) return 1; diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index 9c23c49fdc..0995d6a173 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -29,7 +29,7 @@ Device (SIO) Method (_STA, 0, NotSerialized) { -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) Return (0x0f) #else Return (Zero) diff --git a/src/ec/google/wilco/bootblock.c b/src/ec/google/wilco/bootblock.c index 74578069dc..daf2d7f6c1 100644 --- a/src/ec/google/wilco/bootblock.c +++ b/src/ec/google/wilco/bootblock.c @@ -48,6 +48,6 @@ static void wilco_ec_serial_init(void) void wilco_ec_early_init(void) { - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) wilco_ec_serial_init(); } diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c index 773b8b6ef9..44eea187a8 100644 --- a/src/ec/kontron/kempld/early_kempld.c +++ b/src/ec/kontron/kempld/early_kempld.c @@ -47,7 +47,7 @@ void kempld_release_mutex(void) void kempld_enable_uart_for_console(void) { - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; if (kempld_get_mutex(100) < 0) diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 449fd6ee61..7f592c1bbf 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -318,7 +318,7 @@ Device (HKEY) } } - #if IS_ENABLED(CONFIG_H8_HAS_BAT_TRESHOLDS_IMPL) + #if CONFIG(H8_HAS_BAT_TRESHOLDS_IMPL) #include "thinkpad_bat_thresholds.asl" #endif } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 6e1534c781..de4f2c29b2 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -192,7 +192,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -208,7 +208,7 @@ static void h8_init(struct device *dev) pc_keyboard_init(NO_AUX_DEVICE); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *h8_acpi_name(const struct device *dev) { return "EC"; @@ -216,10 +216,10 @@ static const char *h8_acpi_name(const struct device *dev) #endif struct device_operations h8_dev_ops = { -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_strings = h8_smbios_strings, #endif -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = h8_ssdt_generator, .acpi_name = h8_acpi_name, #endif @@ -312,7 +312,7 @@ static void h8_enable(struct device *dev) if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, val); - val = (IS_ENABLED(CONFIG_H8_SUPPORT_BT_ON_WIFI) || h8_has_bdc(dev)) && + val = (CONFIG(H8_SUPPORT_BT_ON_WIFI) || h8_has_bdc(dev)) && h8_bluetooth_nv_enable(); h8_bluetooth_enable(val); @@ -340,7 +340,7 @@ static void h8_enable(struct device *dev) h8_set_audio_mute(0); -#if !IS_ENABLED(CONFIG_H8_DOCK_EARLY_INIT) +#if !CONFIG(H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif } diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c index fbe0dc052c..4981b861db 100644 --- a/src/ec/lenovo/h8/panic.c +++ b/src/ec/lenovo/h8/panic.c @@ -19,7 +19,7 @@ static void h8_panic(void) { - if (IS_ENABLED(CONFIG_H8_FLASH_LEDS_ON_DEATH)) { + if (CONFIG(H8_FLASH_LEDS_ON_DEATH)) { static const u8 leds[] = { H8_LED_CONTROL_POWER_LED, H8_LED_CONTROL_BAT0_LED, @@ -37,7 +37,7 @@ static void h8_panic(void) ec_write(H8_LED_CONTROL, H8_LED_CONTROL_BLINK | leds[i]); } - if (IS_ENABLED(CONFIG_H8_BEEP_ON_DEATH)) { + if (CONFIG(H8_BEEP_ON_DEATH)) { /* Beep 4 Sec. 1250 Hz */ ec_write(H8_SOUND_ENABLE1, 4); ec_write(H8_SOUND_REPEAT, 1); diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 11a1cb8e7d..af2d3782a2 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -129,7 +129,7 @@ void ec_mem_write(u8 addr, u8 data) #ifndef __SMM__ static void ene_kb3940q_log_events(void) { -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) u8 reason = ec_mem_read(EC_SHUTDOWN_REASON); if (reason) elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason); diff --git a/src/include/adainit.h b/src/include/adainit.h index 34f45cbf8e..4030b37178 100644 --- a/src/include/adainit.h +++ b/src/include/adainit.h @@ -26,7 +26,7 @@ * lizations automatically. When not, we have to call it explicitly. */ -#if IS_ENABLED(CONFIG_RAMSTAGE_ADA) +#if CONFIG(RAMSTAGE_ADA) void ramstage_adainit(void); #else static inline void ramstage_adainit(void) {} diff --git a/src/include/assert.h b/src/include/assert.h index a4ae39f606..afbed03318 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -24,14 +24,14 @@ if (!(x)) { \ printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ ", line %d\n", __FILE__, __LINE__); \ - if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \ + if (CONFIG(FATAL_ASSERTS)) \ hlt(); \ } \ } #define BUG() { \ printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ ", line %d\n", __FILE__, __LINE__); \ - if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \ + if (CONFIG(FATAL_ASSERTS)) \ hlt(); \ } diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 420320e15e..26038c6101 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -115,12 +115,12 @@ struct boot_state_callback { void (*callback)(void *arg); /* For use internal to the boot state machine. */ struct boot_state_callback *next; -#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE) +#if CONFIG(DEBUG_BOOT_STATE) const char *location; #endif }; -#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE) +#if CONFIG(DEBUG_BOOT_STATE) #define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__) #define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC, #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 680284acf1..f3df21d430 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -155,7 +155,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header); * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top() * value stored in nvram to enable early recovery on S3 path. */ -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) void backup_top_of_low_cacheable(uintptr_t ramtop); uintptr_t restore_top_of_low_cacheable(void); #endif @@ -170,7 +170,7 @@ static inline int cbmem_possibly_online(void) if (ENV_BOOTBLOCK) return 0; - if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + if (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return 0; return 1; diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 88e95bbfc6..38495a724d 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -20,9 +20,9 @@ void cbmemc_init(void); void cbmemc_tx_byte(unsigned char data); -#define __CBMEM_CONSOLE_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && \ +#define __CBMEM_CONSOLE_ENABLE__ (CONFIG(CONSOLE_CBMEM) && \ (ENV_RAMSTAGE || ENV_VERSTAGE || ENV_POSTCAR || ENV_ROMSTAGE || \ - (ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)))) + (ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/include/console/console.h b/src/include/console/console.h index 2b02334c8e..2aac832a2a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -22,13 +22,13 @@ #include <console/vtxprintf.h> #include <commonlib/loglevel.h> -#define RAM_DEBUG (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) -#define RAM_SPEW (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) +#define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) +#define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) #ifndef __ROMCC__ void post_code(u8 value); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); struct device; void post_log_path(const struct device *dev); @@ -49,10 +49,10 @@ void __noreturn die(const char *msg); void die_notify(void); #define __CONSOLE_ENABLE__ \ - ((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) || \ - (ENV_POSTCAR && IS_ENABLED(CONFIG_POSTCAR_CONSOLE)) || \ + ((ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \ + (ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \ ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_LIBAGESA || \ - (ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI))) + (ENV_SMM && CONFIG(DEBUG_SMI))) #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); @@ -64,7 +64,7 @@ void do_putchar(unsigned char byte); enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; -#if IS_ENABLED(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) +#if CONFIG(CONSOLE_OVERRIDE_LOGLEVEL) /* * This function should be implemented at mainboard level. * The returned value will _replace_ the loglevel value; diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 1fd5f9117f..6d678f76d0 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -22,7 +22,7 @@ void flashconsole_init(void); void flashconsole_tx_byte(unsigned char c); void flashconsole_tx_flush(void); -#define __CONSOLE_FLASH_ENABLE__ IS_ENABLED(CONFIG_CONSOLE_SPI_FLASH) +#define __CONSOLE_FLASH_ENABLE__ CONFIG(CONSOLE_SPI_FLASH) #if __CONSOLE_FLASH_ENABLE__ static inline void __flashconsole_init(void) { flashconsole_init(); } diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index b52f566896..88590f8ddc 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -22,7 +22,7 @@ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); -#if IS_ENABLED(CONFIG_CONSOLE_NE2K) && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#if CONFIG(CONSOLE_NE2K) && (ENV_ROMSTAGE || ENV_RAMSTAGE) static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 82dbd3fa91..359e01adcf 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -6,7 +6,7 @@ void qemu_debugcon_init(void); void qemu_debugcon_tx_byte(unsigned char data); -#if IS_ENABLED(CONFIG_CONSOLE_QEMU_DEBUGCON) && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#if CONFIG(CONSOLE_QEMU_DEBUGCON) && (ENV_ROMSTAGE || ENV_RAMSTAGE) static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); } static inline void __qemu_debugcon_tx_byte(u8 data) { diff --git a/src/include/console/spi.h b/src/include/console/spi.h index dc88c9ae1d..a425bf4ab3 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -21,8 +21,8 @@ void spiconsole_init(void); void spiconsole_tx_byte(unsigned char c); -#define __CONSOLE_SPI_ENABLE__ (IS_ENABLED(CONFIG_SPI_CONSOLE) && \ - (ENV_RAMSTAGE || (ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI)))) +#define __CONSOLE_SPI_ENABLE__ (CONFIG(SPI_CONSOLE) && \ + (ENV_RAMSTAGE || (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CONSOLE_SPI_ENABLE__ static inline void __spiconsole_init(void) { spiconsole_init(); } diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index f50aca3640..c8c142f380 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -6,7 +6,7 @@ void spkmodem_init(void); void spkmodem_tx_byte(unsigned char c); -#if IS_ENABLED(CONFIG_SPKMODEM) && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#if CONFIG(SPKMODEM) && (ENV_ROMSTAGE || ENV_RAMSTAGE) static inline void __spkmodem_init(void) { spkmodem_init(); } static inline void __spkmodem_tx_byte(u8 data) { spkmodem_tx_byte(data); } #else diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 5c6e679c07..aed67c2c7b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -22,7 +22,7 @@ * baudrate generator. */ unsigned int uart_platform_refclk(void); -#if IS_ENABLED(CONFIG_UART_OVERRIDE_BAUDRATE) +#if CONFIG(UART_OVERRIDE_BAUDRATE) /* Return the baudrate, define this in your platform when using the above configuration. */ unsigned int get_uart_baudrate(void); @@ -63,9 +63,9 @@ static inline void *uart_platform_baseptr(int idx) void oxford_remap(unsigned int new_base); -#define __CONSOLE_SERIAL_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_SERIAL) && \ +#define __CONSOLE_SERIAL_ENABLE__ (CONFIG(CONSOLE_SERIAL) && \ (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ - ENV_POSTCAR || (ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI)))) + ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_init(void) @@ -86,7 +86,7 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) #define CONF_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE static inline void __gdb_hw_init(void) { uart_init(CONF_UART_FOR_GDB); } static inline void __gdb_tx_byte(u8 data) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 4f10a5c5e6..f4f8bd73ed 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -27,10 +27,10 @@ void usb_tx_flush(int idx); unsigned char usb_rx_byte(int idx); int usb_can_rx_byte(int idx); -#define __CONSOLE_USB_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_USB) && \ - ((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \ - (ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \ - (ENV_POSTCAR && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \ +#define __CONSOLE_USB_ENABLE__ (CONFIG(CONSOLE_USB) && \ + ((ENV_BOOTBLOCK && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ + (ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ + (ENV_POSTCAR && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ ENV_RAMSTAGE)) #define USB_PIPE_FOR_CONSOLE 0 @@ -50,8 +50,8 @@ static inline void __usb_tx_flush(void) {} #endif /* */ -#if 0 && IS_ENABLED(CONFIG_GDB_STUB) && \ - ((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) \ +#if 0 && CONFIG(GDB_STUB) && \ + ((ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) \ || ENV_RAMSTAGE) static inline void __gdb_hw_init(void) { usbdebug_init(); } static inline void __gdb_tx_byte(u8 data) diff --git a/src/include/cper.h b/src/include/cper.h index 16040417d3..60cced5852 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -386,7 +386,7 @@ typedef struct cper_ia32x64_ctx_x64state { static inline cper_timestamp_t cper_timestamp(int precise) { cper_timestamp_t ts; -#if IS_ENABLED(CONFIG_RTC) +#if CONFIG(RTC) struct rtc_time time; rtc_get(&time); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index be6708fbbc..8108174ecd 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -45,7 +45,7 @@ static __always_inline unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } -#if !IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT) +#if !CONFIG(AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c */ @@ -142,7 +142,7 @@ void do_lapic_init(void); /* See if I need to initialize the local APIC */ static inline int need_lapic_init(void) { - return IS_ENABLED(CONFIG_SMP) || IS_ENABLED(CONFIG_IOAPIC); + return CONFIG(SMP) || CONFIG(IOAPIC); } static inline void setup_lapic(void) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31c921d93b..5c6cae3a0e 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -105,7 +105,7 @@ typedef struct msrinit_struct { msr_t msr; } msrinit_t; -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) msr_t soc_msr_read(unsigned int index); void soc_msr_write(unsigned int index, msr_t msr); diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 5f968b75fb..fce39b774d 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -4,7 +4,7 @@ #include <console/post_codes.h> -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) #define post_code(value) \ movb $value, %al; \ outb %al, $CONFIG_POST_IO_PORT diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449da61..ffcc2a1958 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -486,7 +486,7 @@ int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); -#if IS_ENABLED(CONFIG_SMM_TSEG) +#if CONFIG(SMM_TSEG) void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); @@ -501,7 +501,7 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#if !IS_ENABLED(CONFIG_SMM_TSEG) +#if !CONFIG(SMM_TSEG) void smi_release_lock(void); #endif diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 35c8a820d5..8dd9b7519c 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,9 +3,9 @@ #include <stdint.h> -#if IS_ENABLED(CONFIG_TSC_SYNC_MFENCE) +#if CONFIG(TSC_SYNC_MFENCE) #define TSC_SYNC "mfence\n" -#elif IS_ENABLED(CONFIG_TSC_SYNC_LFENCE) +#elif CONFIG(TSC_SYNC_LFENCE) #define TSC_SYNC "lfence\n" #else #define TSC_SYNC diff --git a/src/include/device/device.h b/src/include/device/device.h index 4c6706489a..2e2cda9d94 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -52,12 +52,12 @@ struct device_operations { void (*disable)(struct device *dev); void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) int (*get_smbios_data)(struct device *dev, int *handle, unsigned long *current); void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(struct device *dev); @@ -158,7 +158,7 @@ extern struct bus *free_links; extern const char mainboard_name[]; -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) /* IGD UMA memory */ extern uint64_t uma_memory_base; extern uint64_t uma_memory_size; diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 31cdb2bb5b..b1677c8a07 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -52,7 +52,7 @@ * disabled. * @{ */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printram(x, ...) diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 5643787c01..0f9373e220 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -56,7 +56,7 @@ * disabled. * @{ */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printram(x, ...) diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h index c9073967b1..651dc18fbf 100644 --- a/src/include/device/early_smbus.h +++ b/src/include/device/early_smbus.h @@ -52,7 +52,7 @@ /** * \brief printk macro for SMBus debugging */ -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) #define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printsmbus(x, ...) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index c1aea43f78..2fefb39a92 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -15,7 +15,7 @@ #ifndef PCI_H #define PCI_H -#if IS_ENABLED(CONFIG_PCI) +#if CONFIG(PCI) #include <stdint.h> #include <stddef.h> diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 146946ce75..6e5985448a 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -32,7 +32,7 @@ u8 *pci_ehci_base_regs(pci_devfn_t dev); void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); #ifndef __PRE_RAM__ -#if !IS_ENABLED(CONFIG_USBDEBUG) +#if !CONFIG(USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources #else /* Relocation of EHCI Debug Port BAR diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index a13c18b2e1..aaa21813ce 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -69,7 +69,7 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); } -#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) +#if CONFIG(MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index de6cf40c79..2953b25bbb 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -54,7 +54,7 @@ static inline int smbus_write_byte(struct device *const dev, u8 addr, u8 val) int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); -#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) +#if CONFIG(SMBUS_HAS_AUX_CHANNELS) void smbus_switch_to_channel(uint8_t channel_number); uint8_t smbus_get_current_channel(void); #endif diff --git a/src/include/elog.h b/src/include/elog.h index f1d5314ff3..9bb05ade3f 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -231,7 +231,7 @@ struct elog_event_extended_event { u32 event_complement; } __packed; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); extern int elog_clear(void); @@ -264,7 +264,7 @@ static inline int elog_add_extended_event(u8 type, u32 complement) { return 0; } extern u32 gsmi_exec(u8 command, u32 *param); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) u32 boot_count_read(void); #else static inline u32 boot_count_read(void) diff --git a/src/include/gic.h b/src/include/gic.h index f7339a43a7..ab06fc2275 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -16,7 +16,7 @@ #ifndef GIC_H #define GIC_H -#if IS_ENABLED(CONFIG_GIC) +#if CONFIG(GIC) /* Initialize the GIC on the currently processor, including GICD and GICC. */ void gic_init(void); diff --git a/src/include/memlayout.h b/src/include/memlayout.h index b2fbb25af8..1ccb9f7495 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -177,7 +177,7 @@ INCLUDE "verstage/lib/program.ld" #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) \ - _ = ASSERT(IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) == 1, \ + _ = ASSERT(CONFIG(VBOOT_RETURN_FROM_VERSTAGE) == 1, \ "Must set RETURN_FROM_VERSTAGE to overlap romstage."); \ VERSTAGE(addr, size) #else diff --git a/src/include/option.h b/src/include/option.h index f6ede965d8..3a20dcf196 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -6,7 +6,7 @@ * storage can be used. This will benefit machines without CMOS as well as those * without a battery-backed CMOS (e.g. some laptops). */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include <pc80/mc146818rtc.h> #else #include <types.h> diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 5b71c3d1e2..6fa5e46404 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -1,7 +1,7 @@ #ifndef PC80_MC146818RTC_H #define PC80_MC146818RTC_H -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) #include <arch/io.h> #include <types.h> @@ -193,8 +193,8 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) -#if IS_ENABLED(CONFIG_CMOS_POST) -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(CMOS_POST) +#if CONFIG(USE_OPTION_TABLE) # include "option_table.h" # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) #else @@ -241,7 +241,7 @@ static inline void cmos_post_init(void) /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); #endif @@ -254,7 +254,7 @@ static inline void cmos_post_log(void) {} static inline void cmos_post_init(void) {} #endif /* CONFIG_CMOS_POST */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) void sanitize_cmos(void); #else static inline void sanitize_cmos(void) {} diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 7ca457a827..c6fdd523ee 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -369,8 +369,8 @@ struct reg_script_bus_entry { REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) -#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ -IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) +#if CONFIG(SOC_INTEL_BAYTRAIL) || \ +CONFIG(SOC_INTEL_FSP_BAYTRAIL) /* * IO Sideband Function */ diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 4a53daf8a4..bd202488a9 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -69,7 +69,7 @@ struct rmodule { void *relocations; }; -#if IS_ENABLED(CONFIG_RELOCATABLE_MODULES) +#if CONFIG(RELOCATABLE_MODULES) /* Rmodules have an entry point of named _start. */ #define RMODULE_ENTRY(entry_) \ void _start(void *) __attribute__((alias(STRINGIFY(entry_)))) diff --git a/src/include/rules.h b/src/include/rules.h index 8fef53421d..ea8335fb8c 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -275,7 +275,7 @@ /* x86 specific. Indicates that the current stage is running with cache-as-ram * enabled from the beginning of the stage in C code. */ #if defined(__PRE_RAM__) -#define ENV_CACHE_AS_RAM IS_ENABLED(CONFIG_CACHE_AS_RAM) +#define ENV_CACHE_AS_RAM CONFIG(CACHE_AS_RAM) #else #define ENV_CACHE_AS_RAM 0 #endif diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 5db59e9c04..ed70cb7baa 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -1,7 +1,7 @@ #ifndef SMP_ATOMIC_H #define SMP_ATOMIC_H -#if IS_ENABLED(CONFIG_SMP) +#if CONFIG(SMP) #include <arch/smp/atomic.h> #else diff --git a/src/include/smp/node.h b/src/include/smp/node.h index dd5e9f97ac..4dea175ea3 100644 --- a/src/include/smp/node.h +++ b/src/include/smp/node.h @@ -1,7 +1,7 @@ #ifndef _SMP_NODE_H_ #define _SMP_NODE_H_ -#if IS_ENABLED(CONFIG_SMP) +#if CONFIG(SMP) int boot_cpu(void); #else #define boot_cpu(x) 1 @@ -9,7 +9,7 @@ int boot_cpu(void); static inline int is_smp_boot(void) { - return IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1; + return CONFIG(SMP) && CONFIG_MAX_CPUS > 1; } #endif /* _SMP_NODE_H_ */ diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index a7b8001b15..98ab3a778a 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef SMP_SPINLOCK_H #define SMP_SPINLOCK_H -#if IS_ENABLED(CONFIG_SMP) +#if CONFIG(SMP) #include <arch/smp/spinlock.h> #else /* !CONFIG_SMP */ diff --git a/src/include/stddef.h b/src/include/stddef.h index a82a68d189..993d5f09cc 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -36,7 +36,7 @@ typedef unsigned int wint_t; #endif /* Work around non-writable data segment in execute-in-place romstage on x86. */ -#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_ARCH_X86) +#if defined(__PRE_RAM__) && CONFIG(ARCH_X86) #define MAYBE_STATIC #else #define MAYBE_STATIC static diff --git a/src/include/thread.h b/src/include/thread.h index ed04beb8d9..e8041c7a99 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -21,7 +21,7 @@ #include <timer.h> #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if CONFIG(COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__) struct thread { int id; diff --git a/src/include/timer.h b/src/include/timer.h index d3afb19646..621b486594 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -129,7 +129,7 @@ struct stopwatch { static inline void stopwatch_init(struct stopwatch *sw) { - if (IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)) + if (CONFIG(HAVE_MONOTONIC_TIMER)) timer_monotonic_get(&sw->start); else sw->start.microseconds = 0; @@ -153,7 +153,7 @@ static inline void stopwatch_init_msecs_expire(struct stopwatch *sw, long ms) */ static inline void stopwatch_tick(struct stopwatch *sw) { - if (IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)) + if (CONFIG(HAVE_MONOTONIC_TIMER)) timer_monotonic_get(&sw->current); else sw->current.microseconds = 0; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 2074b71408..04d5c12761 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -19,7 +19,7 @@ #include <commonlib/timestamp_serialized.h> -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) +#if CONFIG(COLLECT_TIMESTAMPS) /* * timestamp_init() needs to be called once for each of these cases: * 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and @@ -59,7 +59,7 @@ uint32_t get_us_since_boot(void); /** * Workaround for guard combination above. */ -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) +#if CONFIG(COLLECT_TIMESTAMPS) /* Implemented by the architecture code */ uint64_t timestamp_get(void); #else diff --git a/src/include/trace.h b/src/include/trace.h index 76553ac87b..4f5b8c4e04 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -25,7 +25,7 @@ #else /* !__PRE_RAM__ */ -#if IS_ENABLED(CONFIG_TRACE) && !defined(__SMM__) +#if CONFIG(TRACE) && !defined(__SMM__) void __cyg_profile_func_enter(void *, void *) __attribute__((no_instrument_function)); diff --git a/src/include/watchdog.h b/src/include/watchdog.h index e8de5802ac..e54f3fbf73 100644 --- a/src/include/watchdog.h +++ b/src/include/watchdog.h @@ -1,7 +1,7 @@ #ifndef WATCHDOG_H #define WATCHDOG_H -#if IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) +#if CONFIG(USE_WATCHDOG_ON_BOOT) void watchdog_off(void); #else #define watchdog_off() { while (0); } diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 037e913e93..43674effc7 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -33,7 +33,7 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && + if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) { int i; timestamp_init(base_timestamp); @@ -48,7 +48,7 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, bootblock_soc_early_init(); bootblock_mainboard_early_init(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); } @@ -65,13 +65,13 @@ void main(void) init_timer(); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) base_timestamp = timestamp_get(); bootblock_main_with_timestamp(base_timestamp, NULL, 0); } -#if IS_ENABLED(CONFIG_COMPRESS_BOOTBLOCK) +#if CONFIG(COMPRESS_BOOTBLOCK) /* * This is the bootblock entry point when it is run after a decompressor stage. * For non-decompressor builds, _start is generally defined in architecture- diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 29682eb54d..e402536fde 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -35,7 +35,7 @@ void gfx_set_init_done(int done) int display_init_required(void) { /* For Chrome OS always honor vboot_handoff_skip_display_init(). */ - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) return !vboot_handoff_skip_display_init(); /* By default always initialize display. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 3e2ccf3db4..728674f0da 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -30,7 +30,7 @@ #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if IS_ENABLED(CONFIG_DEBUG_CBFS) +#if CONFIG(DEBUG_CBFS) #define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) #else #define DEBUG(x...) @@ -113,7 +113,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, case CBFS_COMPRESS_LZ4: if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && - !IS_ENABLED(CONFIG_COMPRESS_PRERAM_STAGES)) + !CONFIG(COMPRESS_PRERAM_STAGES)) return 0; /* Load the compressed image to the end of the available memory @@ -133,10 +133,10 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, /* We assume here romstage and postcar are never compressed. */ if (ENV_BOOTBLOCK || ENV_VERSTAGE) return 0; - if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_POSTCAR_STAGE)) + if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) return 0; if ((ENV_ROMSTAGE || ENV_POSTCAR) - && !IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE)) + && !CONFIG(COMPRESS_RAMSTAGE)) return 0; void *map = rdev_mmap(rdev, offset, in_size); if (map == NULL) @@ -255,8 +255,8 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && - IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) { + if (ENV_VERSTAGE && !CONFIG(NO_XIP_EARLY_STAGES) && + CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping); if (mapping == load) @@ -332,7 +332,7 @@ const struct cbfs_locator __weak cbfs_master_header_locator = { extern const struct cbfs_locator vboot_locator; static const struct cbfs_locator *locators[] = { -#if IS_ENABLED(CONFIG_VBOOT) +#if CONFIG(VBOOT) /* * NOTE: Does not link in SMM, as the vboot_locator isn't compiled. * ATM there's no need for VBOOT functionality in SMM and it's not diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index b05b747bf2..32851ca2d9 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -184,7 +184,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) +#if CONFIG(CONSOLE_CBMEM_DUMP_TO_UART) void cbmem_dump_console(void) { struct cbmem_console *cbm_cons_p; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index c2ae0949ed..960ab0f9eb 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -33,11 +33,11 @@ #include <bootmem.h> #include <spi_flash.h> #include <security/vboot/vbnv_layout.h> -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include <option_table.h> #endif -#if IS_ENABLED(CONFIG_CHROMEOS) -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(CHROMEOS) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpi.h> #endif #include <vendorcode/google/chromeos/chromeos.h> @@ -136,7 +136,7 @@ static void lb_framebuffer(struct lb_header *header) struct lb_framebuffer *framebuffer; struct lb_framebuffer fb = {0}; - if (!IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) + if (!CONFIG(LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) return; framebuffer = (struct lb_framebuffer *)lb_new_record(header); @@ -155,7 +155,7 @@ void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, gpios->size += table_size; } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; @@ -196,7 +196,7 @@ static void lb_gpios(struct lb_header *header) static void lb_vbnv(struct lb_header *header) { -#if IS_ENABLED(CONFIG_PC80_SYSTEM) +#if CONFIG(PC80_SYSTEM) struct lb_range *vbnv; vbnv = (struct lb_range *)lb_new_record(header); @@ -207,7 +207,7 @@ static void lb_vbnv(struct lb_header *header) #endif } -#if IS_ENABLED(CONFIG_VBOOT) +#if CONFIG(VBOOT) static void lb_vboot_handoff(struct lb_header *header) { void *addr; @@ -373,7 +373,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) return mainboard; } -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; @@ -489,7 +489,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) head = lb_table_init(rom_table_end); -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) { struct cmos_option_table *option_table = cbfs_boot_map_with_leak("cmos_layout.bin", @@ -516,10 +516,10 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_mainboard(head); /* Record the serial ports and consoles */ -#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) +#if CONFIG(CONSOLE_SERIAL) uart_fill_lb(head); #endif -#if IS_ENABLED(CONFIG_CONSOLE_USB) +#if CONFIG(CONSOLE_USB) lb_add_console(LB_TAG_CONSOLE_EHCI, head); #endif @@ -529,7 +529,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Record our framebuffer */ lb_framebuffer(head); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); @@ -546,7 +546,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_sku_id(head); /* Add SPI flash description if available */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_SPI_FLASH)) lb_spi_flash(head); add_cbmem_pointers(head); @@ -554,7 +554,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Add board-specific table entries, if any. */ lb_board(head); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) lb_ramoops(head); #endif diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 7a5bf3b289..0529d11390 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -52,18 +52,18 @@ void main(void) { init_timer(); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) arg.base_timestamp = timestamp_get(); decompressor_soc_init(); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) arg.timestamps[0].entry_stamp = timestamp_get(); size_t out_size = ulz4f(compressed_bootblock, _bootblock); prog_segment_loaded((uintptr_t)_bootblock, out_size, SEG_FINAL); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) arg.timestamps[1].entry_stamp = timestamp_get(); prog_run(&prog_bootblock); diff --git a/src/lib/edid.c b/src/lib/edid.c index 26a7b52735..553b0a2d7e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -525,7 +525,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, * another call to edid_set_framebuffer_bits_per_pixel(). As a cheap * heuristic, assume that X86 systems require a 64-byte row alignment * (since that seems to be true for most Intel chipsets). */ - if (IS_ENABLED(CONFIG_ARCH_X86)) + if (CONFIG(ARCH_X86)) edid_set_framebuffer_bits_per_pixel(out, 32, 64); else edid_set_framebuffer_bits_per_pixel(out, 32, 0); diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index e4a128e291..d3d0eb0d21 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -6,8 +6,8 @@ void __weak set_boot_successful(void) { } void boot_successful(void) { - if (IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && - IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER)) { + if (CONFIG(FRAMEBUFFER_SET_VESA_MODE) && + CONFIG(VGA_TEXT_FRAMEBUFFER)) { void vbe_textmode_console(void); vbe_textmode_console(); diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 7edc90a221..abeafa5546 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -41,7 +41,7 @@ static FILE *previous_file = NULL; static FILE *fopen(const char *path, const char *mode) { -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "fopen %s with mode %s\n", path, mode); #endif @@ -74,7 +74,7 @@ static FILE *fopen(const char *path, const char *mode) static int fclose(FILE *stream) { -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "fclose %s\n", stream->filename); #endif return 0; @@ -85,7 +85,7 @@ static int fseek(FILE *stream, long offset, int whence) /* fseek should only be called with offset==0 and whence==SEEK_SET * to a freshly opened file. */ gcc_assert(offset == 0 && whence == SEEK_SET); -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "fseek %s offset=%ld whence=%d\n", stream->filename, offset, whence); #endif @@ -96,7 +96,7 @@ static long ftell(FILE *stream) { /* ftell should currently not be called */ gcc_assert(0); -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "ftell %s\n", stream->filename); #endif return 0; @@ -104,7 +104,7 @@ static long ftell(FILE *stream) static size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream) { -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "fread: ptr=%p size=%zd nmemb=%zd FILE*=%p\n", ptr, size, nmemb, stream); #endif @@ -113,7 +113,7 @@ static size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream) static size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream) { -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "fwrite: %zd * %zd bytes to file %s\n", nmemb, size, stream->filename); #endif @@ -145,7 +145,7 @@ static void coverage_init(void *unused) void __gcov_flush(void); static void coverage_exit(void *unused) { -#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) +#if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "Syncing coverage data.\n"); #endif __gcov_flush(); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 98b88418ab..493ff2dcde 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -32,7 +32,7 @@ #include <reset.h> #include <boot/tables.h> #include <program_loading.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif #include <timer.h> @@ -81,7 +81,7 @@ struct boot_state { boot_state_t (*run_state)(void *arg); void *arg; int complete : 1; -#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) +#if CONFIG(HAVE_MONOTONIC_TIMER) struct boot_state_times times; #endif }; @@ -179,7 +179,7 @@ static boot_state_t bs_post_device(void *arg) static boot_state_t bs_os_resume_check(void *arg) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) void *wake_vector; wake_vector = acpi_find_wakeup_vector(); @@ -198,7 +198,7 @@ static boot_state_t bs_os_resume_check(void *arg) static boot_state_t bs_os_resume(void *wake_vector) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); #endif @@ -238,7 +238,7 @@ static boot_state_t bs_payload_boot(void *arg) return BS_PAYLOAD_BOOT; } -#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) +#if CONFIG(HAVE_MONOTONIC_TIMER) static void bs_sample_time(struct boot_state *state) { struct mono_time *mt; @@ -267,7 +267,7 @@ static inline void bs_sample_time(struct boot_state *state) {} static inline void bs_report_time(struct boot_state *state) {} #endif -#if IS_ENABLED(CONFIG_TIMER_QUEUE) +#if CONFIG(TIMER_QUEUE) static void bs_run_timers(int drain) { /* Drain all timer callbacks until none are left, if directed. @@ -295,7 +295,7 @@ static void bs_call_callbacks(struct boot_state *state, phase->callbacks = bscb->next; bscb->next = NULL; -#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE) +#if CONFIG(DEBUG_BOOT_STATE) printk(BIOS_DEBUG, "BS: callback (%p) @ %s.\n", bscb, bscb->location); #endif @@ -339,7 +339,7 @@ static void bs_walk_state_machine(void) break; } - if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)) + if (CONFIG(DEBUG_BOOT_STATE)) printk(BIOS_DEBUG, "BS: Entering %s state.\n", state->name); @@ -359,7 +359,7 @@ static void bs_walk_state_machine(void) next_id = state->run_state(state->arg); - if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)) + if (CONFIG(DEBUG_BOOT_STATE)) printk(BIOS_DEBUG, "BS: Exiting %s state.\n", state->name); @@ -367,7 +367,7 @@ static void bs_walk_state_machine(void) bs_call_callbacks(state, current_phase.seq); - if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)) + if (CONFIG(DEBUG_BOOT_STATE)) printk(BIOS_DEBUG, "----------------------------------------\n"); @@ -448,7 +448,7 @@ void main(void) /* TODO: Understand why this is here and move to arch/platform code. */ /* For MMIO UART this needs to be called before any other printk. */ - if (IS_ENABLED(CONFIG_ARCH_X86)) + if (CONFIG(ARCH_X86)) init_timer(); /* console_init() MUST PRECEDE ALL printk()! Additionally, ensure @@ -470,7 +470,7 @@ void main(void) post_code(POST_ENTRY_RAMSTAGE); /* Handoff sleep type from romstage. */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) acpi_is_wakeup(); #endif diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ff1cb95094..a50d349a87 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -40,8 +40,8 @@ * NULL from cbmem_top() before that point. */ #define CAN_USE_GLOBALS \ - (!IS_ENABLED(CONFIG_ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ - IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)) + (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ + CONFIG(NO_CAR_GLOBAL_MIGRATION)) static inline struct imd *cbmem_get_imd(void) { @@ -303,7 +303,7 @@ void cbmem_get_region(void **baseptr, size_t *size) imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ +#if ENV_RAMSTAGE || (CONFIG(EARLY_CBMEM_LIST) \ && (ENV_POSTCAR || ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 88b3f9be01..b8bcd1c412 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -20,8 +20,8 @@ * <lib.h> in case GCC does not have an assembly version for this arch. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ \ - && !IS_ENABLED(CONFIG_ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */ +#if !CONFIG(ARCH_X86) /* work around lack of --gc-sections on x86 */ \ + && !CONFIG(ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */ int __clzsi2(u32 a); int __clzsi2(u32 a) { diff --git a/src/lib/malloc.c b/src/lib/malloc.c index b881ed2747..aa266b44dc 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -2,7 +2,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> -#if IS_ENABLED(CONFIG_DEBUG_MALLOC) +#if CONFIG(DEBUG_MALLOC) #define MALLOCDBG(x...) printk(BIOS_SPEW, x) #else #define MALLOCDBG(x...) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 7319811fcd..3b77712550 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -68,7 +68,7 @@ void run_romstage(void) prog_run(&romstage); fail: - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + if (CONFIG(BOOTBLOCK_CONSOLE)) die("Couldn't load romstage.\n"); halt(); } @@ -81,7 +81,7 @@ void __weak stage_cache_load_stage(int stage_id, static void ramstage_cache_invalid(void) { printk(BIOS_ERR, "ramstage cache invalid.\n"); - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) { + if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) { board_reset(); } } @@ -113,7 +113,7 @@ static int load_relocatable_ramstage(struct prog *ramstage) static int load_nonrelocatable_ramstage(struct prog *ramstage) { - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + if (CONFIG(HAVE_ACPI_RESUME)) { uintptr_t base = 0; size_t size = cbfs_prog_stage_section(ramstage, &base); if (size) @@ -139,8 +139,8 @@ void run_ramstage(void) * Only x86 systems using ramstage stage cache currently take the same * firmware path on resume. */ - if (IS_ENABLED(CONFIG_ARCH_X86) && - !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (CONFIG(ARCH_X86) && + !CONFIG(NO_STAGE_CACHE)) run_ramstage_from_resume(&ramstage); if (prog_locate(&ramstage)) @@ -148,13 +148,13 @@ void run_ramstage(void) timestamp_add_now(TS_START_COPYRAM); - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (CONFIG(RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (!CONFIG(NO_STAGE_CACHE)) stage_cache_add(STAGE_RAMSTAGE, &ramstage); timestamp_add_now(TS_END_COPYRAM); @@ -190,7 +190,7 @@ void payload_load(void) selfload_check(payload, BM_MEM_RAM); break; case CBFS_TYPE_FIT: /* Flattened image tree */ - if (IS_ENABLED(CONFIG_PAYLOAD_FIT_SUPPORT)) { + if (CONFIG(PAYLOAD_FIT_SUPPORT)) { fit_payload(payload); break; } /* else fall-through */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 156b86255c..851aa75d67 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -35,9 +35,9 @@ *(.text._start); *(.text.stage_entry); #if (ENV_DECOMPRESSOR || ENV_BOOTBLOCK && \ - !IS_ENABLED(CONFIG_COMPRESS_BOOTBLOCK)) && \ - !(IS_ENABLED(CONFIG_ARCH_BOOTBLOCK_X86_32) || \ - IS_ENABLED(CONFIG_ARCH_BOOTBLOCK_X86_64)) + !CONFIG(COMPRESS_BOOTBLOCK)) && \ + !(CONFIG(ARCH_BOOTBLOCK_X86_32) || \ + CONFIG(ARCH_BOOTBLOCK_X86_64)) KEEP(*(.id)); #endif *(.text); @@ -73,7 +73,7 @@ _etext = .; } : to_load -#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +#if ENV_RAMSTAGE && CONFIG(COVERAGE) .ctors . : { . = ALIGN(0x100); __CTOR_LIST__ = .; diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 461a028b11..f0f5c556a6 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -6,7 +6,7 @@ static void write_phys(unsigned long addr, u32 value) { // Assembler in lib/ is very ugly. But we properly guarded // it so let's obey this one for now -#if IS_ENABLED(CONFIG_SSE2) +#if CONFIG(SSE2) asm volatile( "movnti %1, (%0)" : /* outputs */ @@ -31,7 +31,7 @@ static u32 read_phys(unsigned long addr) static void phys_memory_barrier(void) { -#if IS_ENABLED(CONFIG_SSE2) +#if CONFIG(SSE2) // Needed for movnti asm volatile ( "sfence" diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 6234af67d5..50cf7b6d08 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -24,12 +24,12 @@ #include <stdint.h> #include <reg_script.h> -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) #include <cpu/x86/msr.h> #endif -#define HAS_IOSF (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ - IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)) +#define HAS_IOSF (CONFIG(SOC_INTEL_BAYTRAIL) || \ + CONFIG(SOC_INTEL_FSP_BAYTRAIL)) #if HAS_IOSF #include <soc/iosf.h> /* TODO: wrap in <soc/reg_script.h, remove #ifdef? */ @@ -376,7 +376,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) static uint64_t reg_script_read_msr(struct reg_script_context *ctx) { -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) const struct reg_script *step = reg_script_get_step(ctx); msr_t msr = rdmsr(step->reg); uint64_t value = msr.hi; @@ -388,7 +388,7 @@ static uint64_t reg_script_read_msr(struct reg_script_context *ctx) static void reg_script_write_msr(struct reg_script_context *ctx) { -#if IS_ENABLED(CONFIG_ARCH_X86) +#if CONFIG(ARCH_X86) const struct reg_script *step = reg_script_get_step(ctx); msr_t msr; msr.hi = step->value >> 32; diff --git a/src/lib/reset.c b/src/lib/reset.c index 904776e91b..61163f13a3 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -26,7 +26,7 @@ __noreturn void board_reset(void) halt(); } -#if IS_ENABLED(CONFIG_MISSING_BOARD_RESET) +#if CONFIG(MISSING_BOARD_RESET) void do_board_reset(void) { printk(BIOS_CRIT, "No board_reset implementation, hanging...\n"); diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 79bda1ef77..b378d6377e 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -130,11 +130,11 @@ static void smbus_read_spd(u8 *spd, u8 addr) u16 i; u8 step = 1; - if (IS_ENABLED(CONFIG_SPD_READ_BY_WORD)) + if (CONFIG(SPD_READ_BY_WORD)) step = sizeof(uint16_t); for (i = 0; i < SPD_PAGE_LEN; i += step) { - if (IS_ENABLED(CONFIG_SPD_READ_BY_WORD)) + if (CONFIG(SPD_READ_BY_WORD)) ((u16*)spd)[i / sizeof(uint16_t)] = smbus_read_word(0, addr, i); else diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index d2012d4059..b6330fa258 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -114,7 +114,7 @@ static struct timestamp_table *timestamp_alloc_cbmem_table(void) static int timestamp_should_run(void) { /* Only check boot_cpu() in other stages than ramstage on x86. */ - if ((!ENV_RAMSTAGE && IS_ENABLED(CONFIG_ARCH_X86)) && !boot_cpu()) + if ((!ENV_RAMSTAGE && CONFIG(ARCH_X86)) && !boot_cpu()) return 0; return 1; @@ -173,7 +173,7 @@ static void timestamp_add_table_entry(struct timestamp_table *ts_table, tse->entry_id = id; tse->entry_stamp = ts_time - ts_table->base_time; - if (IS_ENABLED(CONFIG_TIMESTAMPS_ON_CONSOLE)) + if (CONFIG(TIMESTAMPS_ON_CONSOLE)) printk(BIOS_SPEW, "Timestamp - %s: %" PRIu64 "\n", timestamp_name(id), ts_time); @@ -250,7 +250,7 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery) /* cbmem is being recovered. */ if (is_recovery) { /* x86 resume path expects timestamps to be reset. */ - if (IS_ENABLED(CONFIG_ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) + if (CONFIG(ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) ts_cbmem_table = timestamp_alloc_cbmem_table(); else { /* Find existing table in cbmem. */ @@ -357,7 +357,7 @@ uint64_t __weak timestamp_get(void) { struct mono_time t1, t2; - if (!IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)) + if (!CONFIG(HAVE_MONOTONIC_TIMER)) return 0; mono_time_set_usecs(&t1, 0); diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index d21b500fa5..837cb138f8 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 92002a6980..efc5913bf9 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb800_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index c805015088..94897c849d 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -83,18 +83,18 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) + if (CONFIG(HUDSON_IMC_FWM)) oem_fan_control(FchParams_env); /* XHCI configuration */ - if (IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE)) + if (CONFIG(HUDSON_XHCI_ENABLE)) FchParams_env->Usb.Xhci0Enable = TRUE; else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index f250168fdd..5201fa3a94 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -34,7 +34,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); -#if IS_ENABLED(CONFIG_HUDSON_UART) +#if CONFIG(HUDSON_UART) configure_hudson_uart(); #endif post_code(0x31); diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index 799455f620..df0a564b76 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -36,7 +36,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 765bb2411e..e134ccdcc0 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb800_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index 318d4a93c6..83db64c60d 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -135,7 +135,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ @@ -272,7 +272,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; @@ -293,7 +293,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) oem_fan_control(FchParams); /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 89d66a5010..6a4da6275f 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -150,7 +150,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -287,7 +287,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); /* Turn on FCH GPP slots */ FchParams->FchReset.GppEnable = TRUE; diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c index 8cb777625c..2cd013b59a 100644 --- a/src/mainboard/amd/lamar/OemCustomize.c +++ b/src/mainboard/amd/lamar/OemCustomize.c @@ -58,7 +58,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER( - IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, + CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, 12, 15 ), PCIE_PORT_DATA_INITIALIZER_V2( @@ -78,7 +78,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { { /* DP3 */ 0, PCIE_ENGINE_DATA_INITIALIZER( - IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, + CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, 12, 15 ), PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4) diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 67b90a41fd..44f6b9402d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 215309b3c5..fa9f7c780f 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index 45dca01829..df13fa502f 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -101,7 +101,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 3eea990349..2f22f6cdfd 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -118,7 +118,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ @@ -256,7 +256,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; @@ -270,7 +270,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) oem_fan_control(FchParams); /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 95b8e41840..506a605905 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -170,7 +170,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index 8375073b06..2eed8b21d3 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -166,7 +166,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 7edc330c80..7ff6caa828 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -152,7 +152,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 0d4b344fe0..61aa9067fc 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -18,7 +18,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index d19ebdadb3..e7421ce2c6 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -245,7 +245,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 4fc97d0e3a..249f301770 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -171,7 +171,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 9e383b4817..96847a74fb 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -152,7 +152,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 0f30f165cf..6bdf94a39d 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -46,7 +46,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index a90bac6ef7..5b66f47f53 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index f8f9d80502..07567aaed6 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,7 +16,7 @@ #define BIOS_SIZE 0x04 //04 - 1MB #endif #define LEGACY_FREE 0x00 -#if !IS_ENABLED(CONFIG_ONBOARD_USB30) +#if !CONFIG(ONBOARD_USB30) #define XHCI_SUPPORT 0x01 #endif diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 622fffec39..557abecb43 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -294,7 +294,7 @@ #define INCHIP_USB_CINFIG 0x7F #define INCHIP_USB_OHCI1_CINFIG 0x01 #define INCHIP_USB_OHCI2_CINFIG 0x01 -#if IS_ENABLED(CONFIG_ONBOARD_USB30) +#if CONFIG(ONBOARD_USB30) #define INCHIP_USB_OHCI3_CINFIG 0x00 #else #define INCHIP_USB_OHCI3_CINFIG 0x01 @@ -962,7 +962,7 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#if IS_ENABLED(CONFIG_ONBOARD_USB30) +#if CONFIG(ONBOARD_USB30) #define SB_XHCI_SWITCH 0 #else #define SB_XHCI_SWITCH 1 diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c index 19296a77b8..3ce6cf3777 100644 --- a/src/mainboard/apple/macbook21/gpio.c +++ b/src/mainboard/apple/macbook21/gpio.c @@ -56,8 +56,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { }; static const struct pch_gpio_set1 pch_gpio_set1_level = { -#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ - IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) +#if CONFIG(BOARD_APPLE_MACBOOK11) || \ + CONFIG(BOARD_APPLE_MACBOOK21) .gpio5 = GPIO_LEVEL_LOW, #else /* CONFIG_BOARD_APPLE_IMAC52 */ .gpio5 = GPIO_LEVEL_HIGH, @@ -72,8 +72,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = { static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio7 = GPIO_INVERT, -#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ - IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) +#if CONFIG(BOARD_APPLE_MACBOOK11) || \ + CONFIG(BOARD_APPLE_MACBOOK21) .gpio13 = GPIO_INVERT, #endif }; @@ -82,7 +82,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; static const struct pch_gpio_set2 pch_gpio_set2_mode = { -#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) +#if CONFIG(BOARD_APPLE_IMAC52) .gpio35 = GPIO_MODE_GPIO, #endif .gpio38 = GPIO_MODE_GPIO, @@ -91,7 +91,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_mode = { }; static const struct pch_gpio_set2 pch_gpio_set2_direction = { -#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) +#if CONFIG(BOARD_APPLE_IMAC52) .gpio35 = GPIO_DIR_OUTPUT, #endif .gpio38 = GPIO_DIR_OUTPUT, @@ -100,7 +100,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_direction = { }; static const struct pch_gpio_set2 pch_gpio_set2_level = { -#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) +#if CONFIG(BOARD_APPLE_IMAC52) .gpio35 = GPIO_LEVEL_LOW, #endif .gpio38 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index 9ae5cf8871..09d5f1ab98 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -19,8 +19,8 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ -#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ - IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) +#if CONFIG(BOARD_APPLE_MACBOOK11) || \ + CONFIG(BOARD_APPLE_MACBOOK21) 0x106b2200, /* Subsystem ID */ 0x0000000B, /* Number of 4 dword sets */ diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl index 09d961d2b4..96870997f5 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl @@ -18,7 +18,7 @@ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 */ -#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0) +#if CONFIG(BOARD_ASROCK_G41M_VS3_R2_0) If (PICM) { Return (Package() { /* PCI1 SLOT 1 */ @@ -53,9 +53,9 @@ If (PICM) { }) } #else -/* IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) \ - || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) \ - || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) */ +/* CONFIG(BOARD_ASROCK_G41C_GS_R2_0) \ + || CONFIG(BOARD_ASROCK_G41C_GS) \ + || CONFIG(BOARD_ASROCK_G41M_GS) */ If (PICM) { Return (Package() { /* PCI1 SLOT 1 */ diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 8474d189a3..8cf34879dd 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -44,7 +44,7 @@ static void mb_lpc_setup(void) setup_pch_gpios(&mainboard_gpio_map); /* Set GPIOs on superio, enable UART */ - if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) { + if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index 3b1c903b3a..eaa27b7957 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -102,7 +102,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index c8cc68a6cb..c01ea74997 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -99,7 +99,7 @@ static const CODEC_TBL_LIST CodecTableList[] = void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams_reset->Mode = 6; /* Read SATA speed setting from CMOS */ diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index f1bf60ea03..e001d43d4a 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -104,8 +104,8 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->SataEnable = 1; FchReset->IdeEnable = 0; diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 45e174c922..9e60ca758a 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -39,7 +39,7 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running * the vendor BIOS. */ -#if !IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE) +#if !CONFIG(BOARD_ASUS_F2A85_M_LE) const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = { {0x11, 0x99430140}, {0x12, 0x411111f0}, @@ -85,7 +85,7 @@ static const CODEC_TBL_LIST CodecTableList[] = void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 9d96753298..ec79fc832b 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -134,8 +134,8 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); } void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) @@ -179,9 +179,9 @@ static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { - if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)) + if (CONFIG(BOARD_ASUS_F2A85_M) || CONFIG(BOARD_ASUS_F2A85_M_PRO)) InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M; - else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)) + else if (CONFIG(BOARD_ASUS_F2A85_M_LE)) InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE; } diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index af8532fdc7..c0aef87a15 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -46,7 +46,7 @@ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ -#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO) +#if CONFIG(BOARD_ASUS_F2A85_M_PRO) Package(){0x000FFFFF, 0, INTA, 0 }, Package(){0x000FFFFF, 1, INTB, 0 }, Package(){0x000FFFFF, 2, INTC, 0 }, diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index e69564ea8e..dc20dc7dd8 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -167,7 +167,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index bed5a731cf..dffb726dc6 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -70,9 +70,9 @@ void board_BeforeAgesa(struct sysinfo *cb) u8 byte; pci_devfn_t dev; - if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); - else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + else if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); /* enable SIO LPC decode */ @@ -95,7 +95,7 @@ void board_BeforeAgesa(struct sysinfo *cb) /* enable SIO clock */ sbxxx_enable_48mhzout(); - if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)) + if (CONFIG(BOARD_ASUS_F2A85_M_PRO)) superio_init_m_pro(); else superio_init_m(); diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c index 52840cac6e..d705b213a2 100644 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; @@ -70,7 +70,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) uint32_t apicid_sp5100; uint32_t apicid_sr5650; - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c index 6cfc93ca93..543ffed9c7 100644 --- a/src/mainboard/asus/kcma-d8/bootblock.c +++ b/src/mainboard/asus/kcma-d8/bootblock.c @@ -33,7 +33,7 @@ void bootblock_mainboard_init(void) pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index 1abca65407..c9b83a0070 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 028af4c938..a74c6dd45c 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -464,7 +464,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_early_setup(); sb7xx_51xx_early_setup(); - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -472,7 +472,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); } - if (IS_ENABLED(CONFIG_SET_FIDVID)) { + if (CONFIG(SET_FIDVID)) { msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -481,7 +481,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -526,7 +526,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); /* Wait for all APs to be stopped, otherwise RAM initialization may hang */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) wait_all_other_cores_stopped(bsp_apicid); /* It's the time to set ctrl in sysinfo now; */ @@ -540,9 +540,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 /* FIXME * After the AMD K10 code has been converted to use - * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + * CONFIG(DEBUG_SMBUS) uncomment this block */ - if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + if (CONFIG(DEBUG_SMBUS)) { dump_spd_registers(&cpu[0]); dump_smbus_registers(); } diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c index ce3d4178da..587e2ff852 100644 --- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -48,7 +48,7 @@ unsigned long acpi_fill_madt(unsigned long current) CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); /* Initialize interrupt mapping if mptable.c didn't. */ - if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) { + if (!CONFIG(GENERATE_MP_TABLE)) { /* Copied from mptable.c */ /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ pci_write_config32(dev, 0x7c, 0x0d800018); diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c index 796ca1a64e..fd57538afa 100644 --- a/src/mainboard/asus/kfsn4-dre/bootblock.c +++ b/src/mainboard/asus/kfsn4-dre/bootblock.c @@ -64,7 +64,7 @@ void bootblock_mainboard_init(void) recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV); if (recovery_enabled) { -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index 82172e82d5..bb51ada9e0 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -74,7 +74,7 @@ void get_bus_conf(void) } } - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index f6faf17152..6ac33f2ccd 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -251,7 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - if (IS_ENABLED(CONFIG_SET_FIDVID)) { + if (CONFIG(SET_FIDVID)) { msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -270,7 +270,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -311,9 +311,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 /* FIXME * After the AMD K10 code has been converted to use - * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + * CONFIG(DEBUG_SMBUS) uncomment this block */ - if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + if (CONFIG(DEBUG_SMBUS)) { dump_spd_registers(&cpu[0]); dump_smbus_registers(); } diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 52840cac6e..d705b213a2 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; @@ -70,7 +70,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) uint32_t apicid_sp5100; uint32_t apicid_sr5650; - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 6cfc93ca93..543ffed9c7 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -33,7 +33,7 @@ void bootblock_mainboard_init(void) pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c index 15d0f500d6..ed01b548db 100644 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ b/src/mainboard/asus/kgpe-d16/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 7e823474e0..7fe9b640ad 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -575,7 +575,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_early_setup(); sb7xx_51xx_early_setup(); - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -583,7 +583,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); } - if (IS_ENABLED(CONFIG_SET_FIDVID)) { + if (CONFIG(SET_FIDVID)) { msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -592,7 +592,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -637,7 +637,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); /* Wait for all APs to be stopped, otherwise RAM initialization may hang */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) wait_all_other_cores_stopped(bsp_apicid); /* It's the time to set ctrl in sysinfo now; */ @@ -651,9 +651,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 /* FIXME * After the AMD K10 code has been converted to use - * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + * CONFIG(DEBUG_SMBUS) uncomment this block */ - if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + if (CONFIG(DEBUG_SMBUS)) { dump_spd_registers(&cpu[0]); dump_smbus_registers(); } diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index ffe283c61a..08ca7150f0 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 3246bdd70a..a53dbecdb2 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -218,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { -#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM) +#if !CONFIG(BOARD_ASUS_M4A785TM) static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index d21b500fa5..837cb138f8 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 899814feeb..42e5c12af9 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb800_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index c59f38cd36..6295a53f1c 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -76,7 +76,7 @@ static int setup_sio_gpio(void) pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); - if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) { + if (CONFIG(BOARD_ASUS_P5QPL_AM)) { /* * P5QPL-AM: * BSEL0 -> not hooked up (not supported anyways) diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index d21b500fa5..837cb138f8 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index f415038162..068fc06d5e 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb800_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 2cfe279960..747b202a3f 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -105,7 +105,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -195,7 +195,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; - if (IS_ENABLED(CONFIG_BAP_E20_DDR3_1066)) + if (CONFIG(BAP_E20_DDR3_1066)) index = 1; else /* CONFIG_BAP_E20_DDR3_800 */ index = 0; diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 8b1fec0a4a..29d01d6355 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -87,7 +87,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 3108dcab17..18e5b7cce6 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -120,7 +120,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ @@ -258,7 +258,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; @@ -272,7 +272,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) oem_fan_control(FchParams); /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; /* sata configuration */ @@ -303,9 +303,9 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; - if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1066)) + if (CONFIG(BAP_E21_DDR3_1066)) index = 1; - else if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1333)) + else if (CONFIG(BAP_E21_DDR3_1333)) index = 2; else /* CONFIG_BAP_E21_DDR3_800 */ index = 0; diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index d1036abc88..7044797a72 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c index 45dca01829..df13fa502f 100644 --- a/src/mainboard/biostar/a68n_5200/OemCustomize.c +++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c @@ -101,7 +101,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index 15834fbedd..e188808423 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -60,10 +60,10 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); - if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); /* enable SIO LPC decode */ diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 7095140646..0390ceaae9 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -94,7 +94,7 @@ static const CODEC_TBL_LIST CodecTableList[] = void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); FchParams_reset->Mode = 6; } diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 6802df7c99..2f7666ee3a 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -103,8 +103,8 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->SataEnable = 1; FchReset->IdeEnable = 0; diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c index a13b966df7..ad758c92cc 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -20,7 +20,7 @@ void bootblock_mainboard_early_init(void) { - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE)) uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD); } diff --git a/src/mainboard/compulab/intense_pc/gpio.c b/src/mainboard/compulab/intense_pc/gpio.c index 373c9f1995..dc98da8e57 100644 --- a/src/mainboard/compulab/intense_pc/gpio.c +++ b/src/mainboard/compulab/intense_pc/gpio.c @@ -74,7 +74,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { }; static const struct pch_gpio_set1 pch_gpio_set1_level = { - #if IS_ENABLED(CONFIG_ENABLE_MSATA) + #if CONFIG(ENABLE_MSATA) .gpio8 = GPIO_LEVEL_LOW, #else .gpio8 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 3cb7067665..dbd28c8aff 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -38,7 +38,7 @@ void pch_enable_lpc(void) /* Map a range for the runtime_port registers to the LPC bus. */ pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) /* Enable COM1 */ if (sio1007_enable_uart_at(SIO_PORT)) { pci_write_config16(dev, LPC_EN, diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 1493565d5e..852800dc4d 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -166,7 +166,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) IORESOURCE_ASSIGNED; } -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int qemu_get_smbios_data16(int handle, unsigned long *current) { struct smbios_type16 *t = (struct smbios_type16 *)*current; @@ -229,7 +229,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = qemu_get_smbios_data, #endif }; diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index 5cfb7c132a..bf918cfa9f 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -22,7 +22,7 @@ */ void main(void) { - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); } diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl index 9432aca833..62470113ea 100644 --- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl +++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl @@ -26,14 +26,14 @@ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e #define IT8720F_SHOW_SP1 1 -#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K) +#if CONFIG(BOARD_FOXCONN_G41S_K) #define IT8720F_SHOW_SP2 1 #endif #define IT8720F_SHOW_EC 1 #define IT8720F_SHOW_KBCK 1 #define IT8720F_SHOW_KBCM 1 #define IT8720F_SHOW_GPIO 1 -#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K) +#if CONFIG(BOARD_FOXCONN_G41S_K) #define IT8720F_SHOW_CIR 1 #endif #include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c index 9ac3c3be6e..bb787b202b 100644 --- a/src/mainboard/foxconn/g41s-k/hda_verb.c +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -17,7 +17,7 @@ #include <device/azalia_device.h> -#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K) +#if CONFIG(BOARD_FOXCONN_G41S_K) const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0888, /* Vendor ID */ diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index e6301df33f..47a7d40fb1 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -82,7 +82,7 @@ static void ich7_enable_lpc(void) void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 -#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K) +#if CONFIG(BOARD_FOXCONN_G41S_K) const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 }; #else /* TODO adapt raminit such that other slots can be used diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 63a4509f88..319417c0d5 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 0de0760637..241e187283 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 497acaaf1e..c98b632ba6 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a974422774..d78564db7d 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 8efe2dfd0a..0c2c81f95e 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index b98b2ac846..6b21f0c177 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -95,7 +95,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 204c1c4ecd..a07ce3e7be 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -16,7 +16,7 @@ #include <variant/onboard.h> -#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY) +#if !CONFIG(BOARD_GOOGLE_BUDDY) Scope (\_SB.PCI0.RP01) { Device (WLAN) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 247fc2fffa..790eeff77c 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -33,7 +33,7 @@ static u8 mainboard_smi_ec(void) u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); @@ -65,7 +65,7 @@ void mainboard_smi_gpi(u32 gpi_sts) static void mainboard_disable_gpios(void) { -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS) +#if CONFIG(BOARD_GOOGLE_SAMUS) /* Put SSD in reset to prevent leak */ set_gpio(BOARD_SSD_RESET_GPIO, 0); /* Disable LTE */ diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index d072fd9cc7..5afb26c5e6 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -131,7 +131,7 @@ static void program_mac_address(u16 io_base) u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index f7b51a9423..4da0a2b6b5 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -69,7 +69,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->tpmp = 1; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) // SuperIO is always RO gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 1d0bc43d84..7286437d46 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -115,7 +115,7 @@ static void program_mac_address(u16 io_base) u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 993c5e82fe..6b6927729b 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -188,7 +188,7 @@ static void mainboard_init(struct device *dev) struct device *ethernet_dev = NULL; void *vpd_file; - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 9f98c8bb7e..726e561e39 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -26,7 +26,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <halt.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index dd6bb6852b..70ab86217b 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -21,6 +21,6 @@ #include <variant/acpi/dptf.asl> /* Include SoC DPTF */ -#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA) +#if !CONFIG(BOARD_GOOGLE_TERRA) #include <acpi/dptf/dptf.asl> #endif diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index e7c91d2080..0db58242f7 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -35,7 +35,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->dpte = 1; /* Disable PMIC I2C port for ACPI for all boards except cyan */ - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) + if (!CONFIG(BOARD_GOOGLE_CYAN)) gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; } diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 752637c015..4b148f8380 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -54,7 +54,7 @@ int get_write_protect_state(void) * in the reading. */ #if ENV_ROMSTAGE - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + if (CONFIG(BOARD_GOOGLE_CYAN)) { write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), @@ -65,7 +65,7 @@ int get_write_protect_state(void) #endif /* WP is enabled when the pin is reading high. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + if (CONFIG(BOARD_GOOGLE_CYAN)) { return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) & PAD_VAL_HIGH); } else { diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 13b83b7f65..397f6d2637 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -37,7 +37,7 @@ DefinitionBlock( Device (PCI0) { #include <acpi/southcluster.asl> -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA) +#if CONFIG(BOARD_GOOGLE_TERRA) #include <variant/acpi/cpu.asl> #else #include <acpi/dptf/cpu.asl> diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index efd20a597f..9ff06391a1 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -33,7 +33,7 @@ void mainboard_ec_init(void) printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) google_chromeec_events_init(&info, acpi_is_wakeup_s3()); post_code(0xf1); diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index ef0f489d0d..aa20593d5f 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -33,7 +33,7 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { /* Update SPD data */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + if (CONFIG(BOARD_GOOGLE_CYAN)) { memory_params->PcdMemoryTypeEnable = MEM_DDR3; memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 88400f7673..852d9c9a33 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -55,14 +55,14 @@ int mainboard_io_trap_handler(int smif) return 1; } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); @@ -89,7 +89,7 @@ static uint8_t mainboard_smi_ec(void) */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) @@ -106,7 +106,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -121,7 +121,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -145,7 +145,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) break; } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); google_chromeec_set_sci_mask(0); @@ -165,7 +165,7 @@ int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { case APM_CNT_ACPI_ENABLE: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) @@ -174,7 +174,7 @@ int mainboard_smi_apmc(uint8_t apmc) #endif break; case APM_CNT_ACPI_DISABLE: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index b7b0c30c5d..af694a4339 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -81,7 +81,7 @@ void mainboard_fill_spd_data(struct pei_data *ps) spd_content = get_spd_pointer(spd_file, spd_file_len / SPD_PAGE_LEN, &dual_channel); - if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) { printk(BIOS_DEBUG, "SPD Data:\n"); hexdump(spd_content, SPD_PAGE_LEN); printk(BIOS_DEBUG, "\n"); @@ -137,7 +137,7 @@ static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) } /* Parse the SPD data to determine the DIMM information */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + if (CONFIG(BOARD_GOOGLE_CYAN)) { dimm->ddr_type = MEMORY_TYPE_DDR3; } else { dimm->ddr_type = MEMORY_TYPE_LPDDR3; diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 2e9ce6382d..ab0b977c87 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index b4cb33238f..4cf2a858c0 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -68,7 +68,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_recovery_mode_switch(void) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) uint64_t ec_events; ec_events = google_chromeec_get_events_b(); diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 9e1a0f31e2..5684f8f867 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -46,7 +46,7 @@ static void mainboard_init(struct device *dev) setup_mmu(DRAM_INITIALIZED); setup_usb(); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Copy WIFI calibration data into CBMEM. */ cbmem_add_vpd_calibration_data(); } @@ -80,7 +80,7 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Retrieve the switch interface MAC addresses. */ lb_table_add_macs_from_vpd(header); } diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index 1a3f5a49bd..1edd8a7020 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -24,7 +24,7 @@ static void ipq_setup_tpm(void) { - if (IS_ENABLED(CONFIG_I2C_TPM)) { + if (CONFIG(I2C_TPM)) { gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_6MA, 1); gpio_set(TPM_RESET_GPIO, 0); diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 476bcf7001..8b04a65c8d 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -73,17 +73,17 @@ static unsigned long mainboard_write_acpi_tables( printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); /* 4 Channel DMIC array. */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH)) + if (CONFIG(NHLT_DMIC_4CH)) if (nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); /* ADI Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_SSM4567) && adi_codec_enable()) + if (CONFIG(NHLT_SSM4567) && adi_codec_enable()) if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add ssm4567.\n"); /* MAXIM Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_MAX98357) && max_codec_enable()) { + if (CONFIG(NHLT_MAX98357) && max_codec_enable()) { if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add max98357.\n"); diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 5eeb583379..81f0866dd6 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -71,6 +71,6 @@ void mainboard_memory_init_params(struct romstage_params *params, sizeof(params->pei_data->RcompTarget)); memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAROLINE)) + if (CONFIG(BOARD_GOOGLE_CAROLINE)) memory_params->DdrFreqLimit = 1600; } diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 5296b0f5cc..a4a1ccadaa 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -60,7 +60,7 @@ __weak void mainboard_gpio_smi_sleep(void) void mainboard_smi_sleep(u8 slp_typ) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); @@ -69,7 +69,7 @@ void mainboard_smi_sleep(u8 slp_typ) int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 41157f0ef3..e9545de625 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -24,7 +24,7 @@ #define GPIO_RESET GPIO(0, B, 3) #define GPIO_SDMMC_PWR GPIO(4, D, 5) -#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) +#if CONFIG(GRU_BASEBOARD_SCARLET) #define GPIO_BL_EN GPIO(4, C, 5) #define GPIO_BACKLIGHT GPIO(4, C, 6) #define GPIO_EC_IN_RW GPIO(0, A, 1) @@ -50,7 +50,7 @@ #define GPIO_WP GPIO(1, C, 2) #endif -#if IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET) +#if CONFIG(GRU_HAS_WLAN_RESET) #define GPIO_WLAN_RST_L GPIO(1, B, 3) #else #define GPIO_WLAN_RST_L dead_code_t(gpio_t, "no WLAN reset on this board in FW") diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 5b2985a7c2..4630a9170b 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -22,7 +22,7 @@ static const int id_readings[] = { /* ID : Volts : ADC value : Bucket */ /* == ===== ========= ========== */ -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) +#if CONFIG(BOARD_GOOGLE_KEVIN) /* 0 : 0.109V: 62 : 0 - 91 */ 91, #else /* 0 : 0.074V: 42 : 0 - 81 */ 81, @@ -80,7 +80,7 @@ uint32_t ram_code(void) uint32_t sku_id(void) { - if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (!CONFIG(GRU_BASEBOARD_SCARLET)) return UNDEFINED_STRAPPING_ID; static uint32_t sku_id = UNDEFINED_STRAPPING_ID; diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 9a716aeaa9..7c18e12fd1 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void) so that we know we can use our GPIOs reliably in following code. */ write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0)); /* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */ - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (CONFIG(GRU_BASEBOARD_SCARLET)) write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3)); /* Reconfigure GPIO1 from dynamic voltage selection through GPIO0_B1 to @@ -46,10 +46,10 @@ void bootblock_mainboard_early_init(void) /* Enable rails powering GPIO blocks, among other things. */ gpio_output(GPIO_P30V_EN, 1); - if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (!CONFIG(GRU_BASEBOARD_SCARLET)) gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + if (CONFIG(CONSOLE_SERIAL)) { _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, "CONSOLE_SERIAL_UART should be UART2"); @@ -89,10 +89,10 @@ static void configure_ec(void) static void configure_tpm(void) { - if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) { + if (CONFIG(GRU_HAS_TPM2)) { rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz); - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { + if (CONFIG(GRU_BASEBOARD_SCARLET)) { gpio_input(GPIO(2, B, 1)); /* SPI2_MISO no-pull */ gpio_input(GPIO(2, B, 2)); /* SPI2_MOSI no-pull */ gpio_input(GPIO(2, B, 3)); /* SPI2_CLK no-pull */ diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 7fb47d0da8..a856e45089 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -21,7 +21,7 @@ #include "board.h" -static const uint32_t wp_polarity = IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) ? +static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ? ACTIVE_LOW : ACTIVE_HIGH; int get_write_protect_state(void) @@ -36,14 +36,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_WP.raw, wp_polarity, gpio_get(GPIO_WP), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, -#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) +#if CONFIG(GRU_BASEBOARD_SCARLET) {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, #endif {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"}, {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, {GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"}, -#if IS_ENABLED(CONFIG_GRU_HAS_TPM2) +#if CONFIG(GRU_HAS_TPM2) {GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"}, #endif }; @@ -53,7 +53,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) void setup_chromeos_gpios(void) { - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (CONFIG(GRU_BASEBOARD_SCARLET)) gpio_input(GPIO_WP); else gpio_input_pullup(GPIO_WP); @@ -61,7 +61,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_EC_IRQ); } -#if IS_ENABLED(CONFIG_GRU_HAS_TPM2) +#if CONFIG(GRU_HAS_TPM2) int tis_plat_irq_status(void) { return gpio_irq_status(GPIO_TPM_IRQ); diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index d4fa7fc381..19f4ecca55 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -97,7 +97,7 @@ static void register_gpio_suspend(void) * 1.5V and 1.8V are EC-controlled on Scarlet derivatives, * so we skip them. */ - if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { + if (!CONFIG(GRU_BASEBOARD_SCARLET)) { static struct bl31_gpio_param param_p15_en = { .h = { .type = PARAM_SUSPEND_GPIO }, .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, @@ -164,7 +164,7 @@ static void configure_sdmmc(void) gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */ /* set SDMMC_DET_L pin */ - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (CONFIG(GRU_BASEBOARD_SCARLET)) /* * do not have external pull up, so need to * set this pin internal pull up @@ -178,7 +178,7 @@ static void configure_sdmmc(void) * In Scarlet derivatives, this GPIO set to high will get 3v, * With other board variants setting this GPIO low results in 3V. */ - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (CONFIG(GRU_BASEBOARD_SCARLET)) gpio_output(GPIO(2, D, 4), 1); else gpio_output(GPIO(2, D, 4), 0); @@ -226,7 +226,7 @@ static void configure_codec(void) write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0); write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); - if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (!CONFIG(GRU_BASEBOARD_SCARLET)) gpio_output(GPIO_P18V_AUDIO_PWREN, 1); gpio_output(GPIO_SPK_PA_EN, 0); @@ -239,7 +239,7 @@ static void configure_display(void) * Rainier is Scarlet-derived, but uses EDP so use board-specific * config rather than baseboard. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { + if (CONFIG(BOARD_GOOGLE_SCARLET)) { gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */ gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */ mdelay(10); @@ -342,9 +342,9 @@ static void mainboard_init(struct device *dev) if (display_init_required()) configure_display(); setup_usb(0); - if (IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET)) + if (CONFIG(GRU_HAS_WLAN_RESET)) assert_wifi_reset(); - if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { + if (!CONFIG(GRU_BASEBOARD_SCARLET)) { configure_touchpad(); /* Scarlet: works differently */ setup_usb(1); /* Scarlet: only one USB port */ } @@ -370,10 +370,10 @@ void mainboard_power_on_backlight(void) gpio_output(GPIO_BL_EN, 1); /* BL_EN */ /* Configure as output GPIO, to be toggled by payload. */ - if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) + if (CONFIG(GRU_BASEBOARD_SCARLET)) gpio_output(GPIO_BACKLIGHT, 0); - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) + if (CONFIG(BOARD_GOOGLE_GRU)) prepare_backlight_i2c(); } diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 0da6539643..6c64990794 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -58,12 +58,12 @@ int scarlet_pwm_design_voltage[][2] = { int pwm_enum_to_pwm_number[] = { [PWM_REGULATOR_GPU] = 0, [PWM_REGULATOR_LIT] = 2, -#if IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM) +#if CONFIG(GRU_HAS_CENTERLOG_PWM) [PWM_REGULATOR_CENTERLOG] = 3, #else [PWM_REGULATOR_CENTERLOG] = -1, #endif -#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) +#if CONFIG(GRU_BASEBOARD_SCARLET) [PWM_REGULATOR_BIG] = 3, #else [PWM_REGULATOR_BIG] = 1, @@ -78,14 +78,14 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) voltage_min = pwm_design_voltage[pwm][0]; voltage_max = pwm_design_voltage[pwm][1]; - if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) || - (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { + if ((CONFIG(BOARD_GOOGLE_KEVIN) && board_id() < 6) || + (CONFIG(BOARD_GOOGLE_GRU) && board_id() < 2)) { voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; - } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { + } else if (CONFIG(BOARD_GOOGLE_KEVIN) && board_id() >= 6) { voltage_min = kevin6_pwm_design_voltage[pwm][0]; voltage_max = kevin6_pwm_design_voltage[pwm][1]; - } else if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { + } else if (CONFIG(GRU_BASEBOARD_SCARLET)) { voltage_min = scarlet_pwm_design_voltage[pwm][0]; voltage_max = scarlet_pwm_design_voltage[pwm][1]; } diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 0b944febc5..57c716590b 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -35,9 +35,9 @@ static void init_dvs_outputs(void) * Kevin's logic rail has some ripple, so up the voltage a bit. Newer * boards use a fixed 900mV regulator for centerlogic. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + if (CONFIG(BOARD_GOOGLE_KEVIN)) pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 925); - else if (IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM)) + else if (CONFIG(GRU_HAS_CENTERLOG_PWM)) pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 900); /* Allow time for the regulators to settle */ diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index e67f0ec2f7..5e9e15f1df 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -51,7 +51,7 @@ enum dram_speeds { static enum dram_speeds get_sdram_target_mhz(void) { - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4) + if (CONFIG(BOARD_GOOGLE_BOB) && board_id() < 4) return dram_800MHz; return dram_928MHz; diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e6321ba1df..243c6270e2 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 9735ca01ad..8a8b223624 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -115,7 +115,7 @@ static void program_mac_address(u16 io_base) u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index d7faafb245..9c3878f3cf 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -21,7 +21,7 @@ void set_power_led(int state) { int polarity; - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) { + if (CONFIG(BOARD_GOOGLE_TIDUS)) { polarity = state == LED_OFF ? 0x00 : 0x01; } else { polarity = state == LED_BLINK ? 0x01 : 0x00; diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index ef807fc64a..3705feb28a 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -47,7 +47,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) init_bootmode_straps(); } diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 8a9e2a61f9..9475361105 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -59,7 +59,7 @@ void mainboard_smi_sleep(u8 slp_typ) set_power_led(LED_BLINK); /* Enable DCP mode */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) { + if (CONFIG(BOARD_GOOGLE_TIDUS)) { set_gpio(GPIO_USB_CTL_1, 0); } break; diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 5c480bf49f..886e14f265 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -58,7 +58,7 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { void OemPostParams(AMD_POST_PARAMS *PostParams) { - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) + if (CONFIG(BOARD_GOOGLE_LIARA)) PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; else diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 8531fc0de2..038cfe22c2 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -34,7 +34,7 @@ void bootblock_mainboard_early_init(void) void bootblock_mainboard_init(void) { - if (IS_ENABLED(CONFIG_EM100)) { + if (CONFIG(EM100)) { /* * We should be able to rely on defaults, but it seems safer * to explicitly set up these registers. diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index 83757a850d..6e823bfa8b 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -24,21 +24,21 @@ void mainboard_smi_gpi(u32 gpi_sts) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) if (gpi_sts & (1 << EC_SMI_GPI)) chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 518d457255..996e6102fc 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -82,7 +82,7 @@ const char *smbios_mainboard_manufacturer(void) static char oem_bin_data[11]; static const char *manuf; - if (!IS_ENABLED(CONFIG_USE_OEM_BIN)) + if (!CONFIG(USE_OEM_BIN)) return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; if (manuf) diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index b1d6736262..ff910fe3e5 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -69,7 +69,7 @@ uint32_t sku_id(void) static uint32_t cached_sku_id = BOARD_ID_INIT; /* On Flapjack, getting the SKU via CBI. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_FLAPJACK)) { + if (CONFIG(BOARD_GOOGLE_FLAPJACK)) { if (cached_sku_id == BOARD_ID_INIT && google_chromeec_cbi_get_sku_id(&cached_sku_id)) cached_sku_id = FLAPJACK_UNDEF_SKU_ID; @@ -77,7 +77,7 @@ uint32_t sku_id(void) } /* Quirk for KUKUI: All P1/SKU0 had incorrectly set SKU=1. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KUKUI)) { + if (CONFIG(BOARD_GOOGLE_KUKUI)) { if (cached_sku_id == BOARD_ID_INIT && board_id() == 1) { cached_sku_id = 0; return cached_sku_id; diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 7d0e9c2d73..81ae9c538d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -24,7 +24,7 @@ void platform_romstage_main(void) { /* This will be done in verstage if CONFIG_VBOOT is enabled. */ - if (!IS_ENABLED(CONFIG_VBOOT)) + if (!CONFIG(VBOOT)) mainboard_early_init(); mt6358_init(); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f6f36117ca..0ff4364574 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -45,7 +45,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 6c896fcc55..04b03bad0a 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <arch/acpi.h> @@ -50,7 +50,7 @@ void mainboard_post(u8 value) */ } -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { int res = 0; @@ -202,7 +202,7 @@ static void mainboard_enable(struct device *dev) dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index f2b55002f8..96ae1cc1c6 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -32,7 +32,7 @@ static u8 mainboard_smi_ec(void) { u8 cmd = google_chromeec_get_event(); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 098ebaf3e8..5cc7f6eef1 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -81,7 +81,7 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); /* This was already called from verstage in vboot context. */ - if (!IS_ENABLED(CONFIG_VBOOT)) + if (!CONFIG(VBOOT)) early_mainboard_init(); run_ramstage(); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 098ebaf3e8..5cc7f6eef1 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -81,7 +81,7 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); /* This was already called from verstage in vboot context. */ - if (!IS_ENABLED(CONFIG_VBOOT)) + if (!CONFIG(VBOOT)) early_mainboard_init(); run_ramstage(); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 35b58d823b..7a1b5fa98a 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -50,7 +50,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; -#if !IS_ENABLED(CONFIG_VBOOT) +#if !CONFIG(VBOOT) configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ @@ -85,7 +85,7 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); /* This was already called from verstage in vboot context. */ - if (!IS_ENABLED(CONFIG_VBOOT)) + if (!CONFIG(VBOOT)) early_mainboard_init(); run_ramstage(); @@ -94,7 +94,7 @@ static void __attribute__((noinline)) romstage(void) /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ void main(void) { -#if !IS_ENABLED(CONFIG_VBOOT) +#if !CONFIG(VBOOT) asm volatile ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); #endif diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3c705e8c1f..4df7eeb047 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -87,7 +87,7 @@ void bootblock_mainboard_init(void) /* Init i2c bus 2 Timing register for TPM */ mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); - if (IS_ENABLED(CONFIG_OAK_HAS_TPM2)) + if (CONFIG(OAK_HAS_TPM2)) gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 666267170a..84d941932b 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -17,7 +17,7 @@ #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ #include <soc/gpio.h> -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN) +#if CONFIG(BOARD_GOOGLE_ROWAN) #define LID GPIO(KPROW1) #define RAM_ID_1 GPIO(DSI_TE) #define RAM_ID_2 GPIO(RDP1_A) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 7ffa746b66..21525fa488 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -127,7 +127,7 @@ static void configure_usb(void) if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) { /* Type C port 0 Over current alert pin */ gpio_input_pullup(GPIO(MSDC3_DSL)); - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) { + if (!CONFIG(BOARD_GOOGLE_ROWAN)) { /* Enable USB3 type A port 0 5V load switch */ gpio_output(GPIO(CM2MCLK), 1); /* USB3 Type A port 0 power over current alert pin */ @@ -150,7 +150,7 @@ static void configure_usb(void) static void configure_usb_hub(void) { - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) + if (CONFIG(BOARD_GOOGLE_ROWAN)) return; /* set usb hub reset pin (low active) to high */ @@ -278,7 +278,7 @@ static void display_startup(void) u32 mipi_dsi_flags; bool dual_dsi_mode; - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) { + if (CONFIG(BOARD_GOOGLE_ROWAN)) { edid = rowan_boe_edid; dual_dsi_mode = true; mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | @@ -327,7 +327,7 @@ static void mainboard_init(struct device *dev) if (display_init_required()) { mtcmos_display_power_on(); - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) { + if (CONFIG(BOARD_GOOGLE_ROWAN)) { configure_backlight_rowan(); configure_display_rowan(); } else { diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 43349a0660..c5bd9963ae 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -37,12 +37,12 @@ void mainboard_save_dimm_info(void) char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; const char *part_num = NULL; - if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) { + if (!CONFIG(DRAM_PART_NUM_IN_CBI)) { save_dimm_info_by_sku_config(); return; } - if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) { + if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back on part numbers encoded in lp4cfg array. */ if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { save_dimm_info_by_sku_config(); diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 0ff376f734..aec2ba2a4f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -205,10 +205,10 @@ static const struct lpddr4_cfg cbi_lp4cfg = { const struct lpddr4_cfg *__weak variant_lpddr4_config(void) { - if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) + if (!CONFIG(DRAM_PART_NUM_IN_CBI)) return &non_cbi_lp4cfg; - if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) { + if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back non cbi memory config. */ if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) return &non_cbi_lp4cfg; diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index b73bbc9456..914f71c50d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -32,13 +32,13 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints. */ - if (IS_ENABLED(CONFIG_NHLT_DA7219)) { + if (CONFIG(NHLT_DA7219)) { /* Dialog for Headset codec */ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (IS_ENABLED(CONFIG_NHLT_RT5682)) { + if (CONFIG(NHLT_RT5682)) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 61dcde10f0..7d196e9400 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -47,7 +47,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index e49dfce2b1..5883cdcae9 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,7 +29,7 @@ static u8 mainboard_smi_ec(void) { u8 src; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static int battery_critical_logged; #endif @@ -39,7 +39,7 @@ static u8 mainboard_smi_ec(void) switch (src) { case EC_BATTERY_CRITICAL: -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); @@ -49,7 +49,7 @@ static u8 mainboard_smi_ec(void) case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ @@ -70,7 +70,7 @@ void mainboard_smi_gpi(u32 gpi_sts) else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 0001867988..34862df3cb 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_VARIANT_HAS_CAMERA_ACPI) +#if CONFIG(VARIANT_HAS_CAMERA_ACPI) /* Camera */ #include <variant/acpi/camera.asl> #endif diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 6802de9783..59eeefb27e 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <arch/acpi.h> @@ -37,7 +37,7 @@ void mainboard_suspend_resume(void) { } -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { int res = 1; @@ -126,7 +126,7 @@ static int int15_handler(void) static void mainboard_init(struct device *dev) { mainboard_ec_init(); -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO) +#if CONFIG(BOARD_GOOGLE_NINJA) || CONFIG(BOARD_GOOGLE_SUMO) lan_init(); #endif } @@ -166,7 +166,7 @@ static void mainboard_enable(struct device *dev) dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 113e7ce987..94f7b2b4cc 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -34,7 +34,7 @@ static uint8_t mainboard_smi_ec(void) uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 87df672c67..93ecc3ab5e 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -114,7 +114,7 @@ static void program_mac_address(u16 io_base) u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 5dae431297..9a3c1301c8 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -114,7 +114,7 @@ static void program_mac_address(u16 io_base) u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index 6bc519078a..1743860a37 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -38,14 +38,14 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(slp_typ, &num); gpio_configure_pads(pads, num); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index 8e42b930b1..f2ef80fbe3 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -23,15 +23,15 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + if (CONFIG(NHLT_DMIC_1CH_16B) && (!nhlt_soc_add_dmic_array(nhlt, 1))) printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + if (CONFIG(NHLT_DMIC_2CH_16B) && (!nhlt_soc_add_dmic_array(nhlt, 2))) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); /* 4-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + if (CONFIG(NHLT_DMIC_4CH_16B) && (!nhlt_soc_add_dmic_array(nhlt, 4))) printk(BIOS_ERR, "Added 4CH DMIC array.\n"); /* Dialog for Headset codec. diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index 73de67e525..950a029459 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -56,7 +56,7 @@ uint8_t variant_board_sku(void) board_sku_num = sku_strapping_value(); - if (!IS_ENABLED(CONFIG_CHROMEOS)) + if (!CONFIG(CHROMEOS)) return board_sku_num; if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_ANY)) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 642e2403dd..e5b0ccad2e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -42,7 +42,7 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* VPD support */ @@ -57,7 +57,7 @@ DefinitionBlock( /* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> -#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO) +#if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/sarien/variants/sarien/ramstage.c b/src/mainboard/google/sarien/variants/sarien/ramstage.c index ab79678f9a..d20260cc91 100644 --- a/src/mainboard/google/sarien/variants/sarien/ramstage.c +++ b/src/mainboard/google/sarien/variants/sarien/ramstage.c @@ -43,7 +43,7 @@ static void disable_unused_touchscreen(void *unused) struct drivers_i2c_hid_config *info; /* Look for VPD key that indicates which touchscreen is present */ - if (IS_ENABLED(CONFIG_VPD) && + if (CONFIG(VPD) && !vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid, ARRAY_SIZE(touchscreen_hid), VPD_ANY)) printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n", diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 0ffd054695..c748fb4ad3 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -52,7 +52,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->tpmp = 1; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index bab764a714..81a772c06b 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -41,7 +41,7 @@ static u8 mainboard_smi_ec(void) u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 162456e00a..37d49bd00e 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -217,7 +217,7 @@ struct chip_operations mainboard_ops = { void lb_board(struct lb_header *header) { -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) lb_table_add_serialno_from_vpd(header); #endif soc_add_mtc(header); diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index b5dbbeadb4..fdff5ab0f4 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -31,7 +31,7 @@ static void setup_usb(void) { -#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148) +#if !CONFIG(BOARD_VARIANT_AP148) gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); gpio_set(USB_ENABLE_GPIO, 1); @@ -90,7 +90,7 @@ static void mainboard_init(struct device *dev) /* Functionally a 0-cost no-op if NAND is not present */ board_nand_init(); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Copy WIFI calibration data into CBMEM. */ cbmem_add_vpd_calibration_data(); #endif @@ -124,7 +124,7 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Retrieve the switch interface MAC addresses. */ lb_table_add_macs_from_vpd(header); #endif diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 9fbdcfcd33..083045678e 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -49,7 +49,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 6c895085c2..a54b80b633 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -75,7 +75,7 @@ void stout_ec_finalize_smm(void) if (ec_reg & 0x8) { printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR); #endif } @@ -85,7 +85,7 @@ void stout_ec_finalize_smm(void) if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL); #endif } @@ -97,14 +97,14 @@ void stout_ec_finalize_smm(void) if ((ec_reg & 0xCF) == 0xC0) { printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); #endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY); #endif } diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index 1158411654..3eaad3451e 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -22,7 +22,7 @@ static void mainboard_init(struct device *dev) { -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Copy WIFI calibration data into CBMEM. */ cbmem_add_vpd_calibration_data(); #endif @@ -48,7 +48,7 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Retrieve the switch interface MAC addresses. */ lb_table_add_macs_from_vpd(header); #endif diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index 604b399676..c9c68ccd5b 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -38,7 +38,7 @@ uint32_t ram_code(void) gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ - if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE)) + if (CONFIG(VEYRON_FORCE_BINARY_RAM_CODE)) code = gpio_base2_value(pins, ARRAY_SIZE(pins)); else code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 4c2f1439b6..86834bfd71 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -31,7 +31,7 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index d9a07e73d2..18047f28f9 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -31,7 +31,7 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 909a8efb8f..73f57d15ec 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -31,7 +31,7 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index f3c5515d8c..424b68a936 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -96,7 +96,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c index a1b5a0938d..2d6499f9dd 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c @@ -19,7 +19,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -45,7 +45,7 @@ static void mainboard_enable(struct device *dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) dev->ops->get_smbios_data = mainboard_smbios_data; #endif } diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 6ea302df5e..4b640689b7 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -69,7 +69,7 @@ void mainboard_early_init(int s3resume) void mainboard_config_superio(void) { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index f6c72dadb3..f204632078 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -30,7 +30,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 7eaff5705f..66c480ebad 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); #endif -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 9c6c9b68f7..2b1ac04159 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -170,7 +170,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 11d6c6a817..43786af295 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -167,7 +167,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 7ab5eb1221..c6d62ed542 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 942941d85f..30c1026c16 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -38,7 +38,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 734679df26..ea67b62938 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); - #if IS_ENABLED(CONFIG_SET_FIDVID) + #if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 631adea496..f013f698d6 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -122,7 +122,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mupd->FspmConfig.LowMemoryMaxValue = 0; mupd->FspmConfig.HighMemoryMaxValue = 0; - if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + if (CONFIG(BOARD_INTEL_APOLLOLAKE_RVP1)) rvp1_fill_memory_params(mupd); else rvp2_fill_memory_params(mupd); diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index c5293dc9dd..af2101f506 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -71,7 +71,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->tpmp = 1; -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Emerald Lake has no EC (?) */ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 94248557bf..328087847a 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <arch/interrupt.h> diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index c34d82fde1..0b8c16b702 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -163,7 +163,7 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; /* Disable 2nd DIMM on Bakersport*/ -#if IS_ENABLED(CONFIG_BOARD_INTEL_BAKERSPORT_FSP) +#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP) UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ #endif } diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index 946a45362a..88cfb1d26f 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <arch/interrupt.h> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 88b69da1cd..c719d2388f 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -39,7 +39,7 @@ DefinitionBlock( } } - #if IS_ENABLED(CONFIG_CHROMEOS) + #if CONFIG(CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 390929e692..5ceff51f44 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -44,7 +44,7 @@ void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); @@ -57,7 +57,7 @@ void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index a1354da7e0..2455422b74 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -163,7 +163,7 @@ static const struct pad_config gpio_table[] = { /* D23 : SPP_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCIE_0_SATAGP_0 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) +#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY) PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), #endif /* E1 : SATAXPCIE_1_SATAGP_1 */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c index f3be0e8435..343b721031 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c @@ -21,19 +21,19 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + if (CONFIG(NHLT_DMIC_1CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 1)) printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + if (CONFIG(NHLT_DMIC_2CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); /* 4-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + if (CONFIG(NHLT_DMIC_4CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) + if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) { /* Dialog for Headset codec. * Headset codec is bi-directional but uses the same configuration @@ -47,7 +47,7 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); } - if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) && + if (CONFIG(INCLUDE_SND_MAX98373_NHLT) && !nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1)) printk(BIOS_ERR, "Added Maxim_98373 codec.\n"); } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 2ccf3b7f4f..70d0bd6ded 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -39,7 +39,7 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index fc350509e3..b0091bd41a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -17,7 +17,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) static const struct pad_config gpio_table[] = { /* GPPC */ /* A0 : RCINB_TIME_SYNC_1 */ @@ -264,7 +264,7 @@ static const struct pad_config gpio_table[] = { /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) +#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c index 161cc5f55f..34b161f919 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c @@ -21,19 +21,19 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + if (CONFIG(NHLT_DMIC_1CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 1)) printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + if (CONFIG(NHLT_DMIC_2CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); /* 4-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + if (CONFIG(NHLT_DMIC_4CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) { + if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) { /* Dialog for Headset codec. * Headset codec is bi-directional but uses the same * configuration settings for render and capture endpoints. @@ -46,7 +46,7 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); } - if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) && + if (CONFIG(INCLUDE_SND_MAX98373_NHLT) && !nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1)) printk(BIOS_ERR, "Added Maxim_98373 codec.\n"); } diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 8adc853c62..20c71a333b 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -19,7 +19,7 @@ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x4e -#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if !CONFIG(DISABLE_UART_ON_TESTPADS) #define NCT6776_SHOW_SP1 1 #endif #define NCT6776_SHOW_HWM 1 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 1a46f8bbab..510073540f 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -27,7 +27,7 @@ #include "superio.h" #include "thermal.h" -#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if CONFIG(DISABLE_UART_ON_TESTPADS) #define DEBUG_UART_EN 0 #else #define DEBUG_UART_EN COMA_LPC_EN @@ -46,7 +46,7 @@ void mainboard_rcba_config(void) /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) /* Enable Gigabit Ethernet */ if (RCBA32(BUC) & PCH_DISABLE_GBE) { RCBA32(BUC) &= ~PCH_DISABLE_GBE; @@ -125,7 +125,7 @@ static const u16 superio_initvals[] = { SUPERIO_INITVAL(0x1a, 0x02), SUPERIO_INITVAL(0x1b, 0x6a), SUPERIO_INITVAL(0x27, 0x80), -#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if CONFIG(DISABLE_UART_ON_TESTPADS) SUPERIO_INITVAL(0x2a, 0x80), #else SUPERIO_INITVAL(0x2a, 0x00), diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index ad31bba5ab..24ec912a4c 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -18,13 +18,13 @@ #include <stdint.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) #include <northbridge/intel/sandybridge/raminit_native.h> #else #include <northbridge/intel/sandybridge/raminit.h> #endif -#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 1791ee3e96..1fd7fce0c7 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -25,15 +25,15 @@ void car_mainboard_pre_console_init(void) const struct reg_script *script; /* Initialize the GPIO controllers */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) script = gen2_gpio_init; else script = gen1_gpio_init; reg_script_run(script); /* Initialize the RXD and TXD paths for UART0 */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) { - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(ENABLE_BUILTIN_HSUART0)) { + if (CONFIG(GALILEO_GEN2)) script = gen2_hsuart0; else script = (reg_legacy_gpio_read( @@ -51,7 +51,7 @@ void mainboard_gpio_i2c_init(struct device *dev) printk(BIOS_INFO, "Galileo I2C chip initialization\n"); /* Determine the correct script for the board */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) script = gen2_i2c_init; else /* Determine which I2C address is in use */ @@ -69,7 +69,7 @@ void mainboard_gpio_pcie_reset(uint32_t pin_value) uint32_t value; /* Determine the correct PCIe reset pin */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO; else pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO; diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c index 2a8ade7116..0237916e17 100644 --- a/src/mainboard/intel/galileo/mainboard.c +++ b/src/mainboard/intel/galileo/mainboard.c @@ -18,7 +18,7 @@ /* Set the board version */ const char *smbios_mainboard_version(void) { - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) return "Gen 2"; return "1.0"; } diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index a5b74a08dc..b78ed1bd3e 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -60,7 +60,7 @@ void verstage_mainboard_init(void) */ /* Determine the correct script for the board */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) script = gen2_i2c_init; else /* Determine which I2C address is in use */ @@ -86,7 +86,7 @@ void __weak vboot_platform_prepare_reboot(void) */ /* Determine the correct script for the board */ - if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + if (CONFIG(GALILEO_GEN2)) script = gen2_tpm_reset; else /* Determine which I2C address is in use */ diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 9c5aa6daf7..0676eaca32 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -27,7 +27,7 @@ uint32_t board_id(void) { MAYBE_STATIC int id = -1; if (id < 0) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) id = variant_board_id(); else { if (send_ec_command(EC_FAB_ID_CMD) == 0) diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index 0138a9c234..44b7824224 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -54,7 +54,7 @@ static void bootblock_ec_init(void) void mainboard_ec_init(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (ENV_RAMSTAGE) ramstage_ec_init(); else if (ENV_BOOTBLOCK) @@ -69,7 +69,7 @@ void mainboard_ec_init(void) | LPC_IOE_LGE_200); } - if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) { + if (CONFIG(GLK_INTEL_EC)) { printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n"); outb(0xaa, 0x66); printk(BIOS_INFO, "Hack to turn on the CPU fan\n"); diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 8e135903dc..7811d06044 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -211,7 +211,7 @@ static void fill_memory_params(FSP_M_CONFIG *cfg) { uint8_t boardid; - if (IS_ENABLED(CONFIG_IS_GLK_RVP_1)) + if (CONFIG(IS_GLK_RVP_1)) boardid = BOARD_ID_GLK_RVP1_DDR4; else boardid = BOARD_ID_GLK_RVP2_LP4; diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index f6d98e5f20..9af899398f 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -25,7 +25,7 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) if (gpi_status_get(sts, EC_SMI_GPI)) chromeec_smi_process_events(); } @@ -38,14 +38,14 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; @@ -53,6 +53,6 @@ int mainboard_smi_apmc(u8 apmc) void mainboard_smi_espi_handler(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_process_events(); } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 8df1dc4c60..69a0a9116a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -21,7 +21,7 @@ int variant_board_id(void) { MAYBE_STATIC uint32_t id = BOARD_ID_INIT; - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (id == BOARD_ID_INIT) { if (google_chromeec_get_board_version(&id)) id = BOARD_ID_UNKNOWN; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 03f2147006..3cbb4bcd44 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */ -#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI) +#if CONFIG(TPM_ON_FAST_SPI) PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */ #endif PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/ diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index dc23abd2fc..170e87c988 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -22,7 +22,7 @@ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 * which is North community */ -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) #define EC_SCI_GPI GPE0A_ESPI_SCI_STS #else #define EC_SCI_GPI GPE0_DW1_05 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c index 5433bd571c..c35a2923f5 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c @@ -21,15 +21,15 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + if (CONFIG(NHLT_DMIC_1CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 1)) printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + if (CONFIG(NHLT_DMIC_2CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); /* 4-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + if (CONFIG(NHLT_DMIC_4CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Added 4CH DMIC array.\n"); diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index e3a0a01166..44fdc4f467 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -22,7 +22,7 @@ #include <fsp/soc_binding.h> #include <string.h> -#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN) +#if CONFIG(ENABLE_FSP_MEMORY_DOWN) /* * Define platform specific Memory Down Configure structure. @@ -118,7 +118,7 @@ void mainboard_config_gpios(void) void mainboard_memory_init_params(FSPM_UPD *mupd) { -#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN) +#if CONFIG(ENABLE_FSP_MEMORY_DOWN) uint8_t *spd_data_ptr = NULL; /* Get SPD data pointer */ diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl index 49ae2e6ff4..ef2e164c93 100644 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c index 6ac312ad8d..b56f047008 100644 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -34,7 +34,7 @@ int get_board_id(void) MAYBE_STATIC int id = -1; if (id < 0) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) id = get_board_id_via_ext_ec(); else{ uint8_t buffer[2]; diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 53feeb9e96..ad469faaa7 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -43,12 +43,12 @@ DefinitionBlock( } } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index a9a61ddc2c..efed4de820 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,7 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 544d695811..531cd21336 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index d48c9c238b..101b04be74 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -43,7 +43,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) /* Read lid switch state from the EC. */ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); @@ -53,7 +53,7 @@ int get_lid_switch(void) int get_recovery_mode_switch(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* Check for dedicated recovery switch first. */ if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) @@ -70,7 +70,7 @@ int get_recovery_mode_switch(void) int clear_recovery_mode_switch(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) /* Clear keyboard recovery event. */ return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index ddb69da97d..8a165518b7 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -51,7 +51,7 @@ DefinitionBlock( #include "acpi/ipu_mainboard.asl" #include "acpi/mipi_camera.asl" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c index bbe0af027b..fdd196dc88 100644 --- a/src/mainboard/intel/kblrvp/hda_verb.c +++ b/src/mainboard/intel/kblrvp/hda_verb.c @@ -14,6 +14,6 @@ * GNU General Public License for more details. */ -#if !IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) +#if !CONFIG(BOARD_INTEL_KBLRVP8) #include "variant/hda_verb.h" #endif diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 38279c3313..604c069d77 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -27,7 +27,7 @@ static void mainboard_init(struct device *dev) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index 0b52f377be..ad55c2675a 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -32,7 +32,7 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) static void ioexpander_init(void *unused) { - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) + if (CONFIG(BOARD_INTEL_KBLRVP11)) return; printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 8e5ffcf955..c96f791516 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -42,7 +42,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + if (CONFIG(BOARD_INTEL_KBLRVP3)) { struct region_device spd_rdev; mem_cfg->DqPinsInterleaved = 0; diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index bb09d78da2..ba8458be15 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -47,25 +47,25 @@ int mainboard_io_trap_handler(int smif) void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) + if (CONFIG(BOARD_INTEL_KBLRVP8)) return; - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) if (gpi_status_get(sts, EC_SMI_GPI)) chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 64cc34b6d6..df02601368 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -54,14 +54,14 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) void mainboard_smi_sleep(u8 slp_typ) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index efd20a597f..9ff06391a1 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -33,7 +33,7 @@ void mainboard_ec_init(void) printk(BIOS_DEBUG, "mainboard_ec_init\n"); post_code(0xf0); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) google_chromeec_events_init(&info, acpi_is_wakeup_s3()); post_code(0xf1); diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 6cd01e2b33..052e830171 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -54,14 +54,14 @@ int mainboard_io_trap_handler(int smif) return 1; } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) static uint8_t mainboard_smi_ec(void) { uint8_t cmd = google_chromeec_get_event(); uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); @@ -88,7 +88,7 @@ static uint8_t mainboard_smi_ec(void) */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) @@ -102,7 +102,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -117,7 +117,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) if (smm_get_gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); @@ -131,7 +131,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) break; } -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) /* Disable SCI and SMI events */ google_chromeec_set_smi_mask(0); google_chromeec_set_sci_mask(0); @@ -150,7 +150,7 @@ int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { case APM_CNT_ACPI_ENABLE: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_smi_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) @@ -159,7 +159,7 @@ int mainboard_smi_apmc(uint8_t apmc) #endif break; case APM_CNT_ACPI_DISABLE: -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0) diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index ade9c79e00..cbf436bf6f 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -37,7 +37,7 @@ void get_bus_conf(void) pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; /* I/O APICs: APIC ID Version State Address */ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 588203c242..e8126d5913 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if IS_ENABLED(CONFIG_LOGICAL_CPUS) + #if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index c2a8721bba..26e02a0739 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -29,7 +29,7 @@ #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { int res = 0; @@ -162,8 +162,8 @@ static int int15_handler(void) static void mainboard_enable(struct device *dev) { -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) || \ - IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) || \ + CONFIG(PCI_OPTION_ROM_RUN_REALMODE) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 9c6c9b68f7..2b1ac04159 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -102,7 +102,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { /* Enable IMC fan control. the recommand way */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -170,7 +170,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index e61dd4a45d..f842129ae2 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -174,7 +174,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = FALSE; } diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 3eaa8b07fb..c3e40ce16f 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index f4830fcd8e..03ee4dba06 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -43,7 +43,7 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); /* Enable external USB port power. */ - if (IS_ENABLED(CONFIG_USBDEBUG)) + if (CONFIG(USBDEBUG)) ec_mm_set_bit(0x3b, 4); } diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index c502d6a601..b3cac1d21e 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -65,7 +65,7 @@ static const CODEC_TBL_LIST CodecTableList[] = void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 98b3478dc4..4782e11271 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -150,8 +150,8 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); } void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index f160745fcd..9e57e39613 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -167,7 +167,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 29880f48fd..0266eff5c4 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,9 +117,9 @@ void board_BeforeAgesa(struct sysinfo *cb) u8 byte; pci_devfn_t dev; - if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); - else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + else if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); /* enable SIO LPC decode */ diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 8c7f921041..74b14b42c8 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ab9b0a4594..11015f6a67 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a208ee..93c2a58f74 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,7 +15,7 @@ */ #include <device/device.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c index f1a3a208ee..93c2a58f74 100644 --- a/src/mainboard/ocp/wedge100s/mainboard.c +++ b/src/mainboard/ocp/wedge100s/mainboard.c @@ -15,7 +15,7 @@ */ #include <device/device.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index b8da280e9b..7fdc981915 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -38,7 +38,7 @@ void early_mainboard_romstage_entry(void) pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1); - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -76,7 +76,7 @@ void late_mainboard_romstage_entry(void) void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr; - if (IS_ENABLED(CONFIG_FSP_USES_UPD)) { + if (CONFIG(FSP_USES_UPD)) { /* The internal UART operates on 0x3f8/0x2f8. * As it's not wired up and conflicts with SuperIO decoding * the same range, make sure to disable it. @@ -91,7 +91,7 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) fsp_upd_data->SerialPortBaudRate = 0; /* Make FSP use serial IO */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) fsp_upd_data->SerialPortType = 1; else fsp_upd_data->SerialPortType = 0; diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c index 9dfd1b8ba3..c7f2639d4d 100644 --- a/src/mainboard/opencellular/elgon/bootblock.c +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -31,7 +31,7 @@ void bootblock_mainboard_early_init(void) /* Turn off error LED */ gpio_output(ELGON_GPIO_ERROR_LED, 0); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE)) uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD); } diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 8a960cf6c7..3faa462cf1 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -72,7 +72,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; @@ -85,13 +85,13 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) oem_fan_control(FchParams); /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)) { + if (CONFIG(BOARD_PCENGINES_APU2)) { // Disable EHCI 0 (port 0 to 3) FchParams->Usb.Ehci1Enable = FALSE; } else { diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 16bbf8a76b..472b864bd9 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -142,16 +142,16 @@ static void config_gpio_mux(void) uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); if (uart) - uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_C); + uart->enabled = CONFIG(APU2_PINMUX_UART_C); if (gpio) - gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO0); + gpio->enabled = CONFIG(APU2_PINMUX_GPIO0); uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); if (uart) - uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_D); + uart->enabled = CONFIG(APU2_PINMUX_UART_D); if (gpio) - gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO1); + gpio->enabled = CONFIG(APU2_PINMUX_GPIO1); } /********************************************** diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 49281b905a..c449cc1ae9 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -79,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* COM2 on apu5 is reserved so only COM1 should be supported */ if ((CONFIG_UART_FOR_CONSOLE == 1) && - !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) + !CONFIG(BOARD_PCENGINES_APU5)) nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); else if (CONFIG_UART_FOR_CONSOLE == 0) nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); @@ -143,13 +143,13 @@ static void early_lpc_init(void) // // Configure output disabled, value low, pull up/down disabled // - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { + if (CONFIG(BOARD_PCENGINES_APU5)) { configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting); } - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { + if (CONFIG(BOARD_PCENGINES_APU2) || + CONFIG(BOARD_PCENGINES_APU3) || + CONFIG(BOARD_PCENGINES_APU4)) { configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); } @@ -161,8 +161,8 @@ static void early_lpc_init(void) // Configure output enabled, value low, pull up/down disabled // setting = GPIO_OUTPUT_ENABLE; - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { + if (CONFIG(BOARD_PCENGINES_APU3) || + CONFIG(BOARD_PCENGINES_APU4)) { configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); } @@ -175,7 +175,7 @@ static void early_lpc_init(void) // setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE; - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { + if (CONFIG(BOARD_PCENGINES_APU5)) { configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); } diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index e1364b6cef..0c3d3dbb61 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <ec/acpi/ec.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1bb0b797d7..74d491f310 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -30,7 +30,7 @@ #include <southbridge/intel/common/gpio.h> #include <halt.h> #include "option_table.h" -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif @@ -39,7 +39,7 @@ void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 8370cfe0a8..9450aa1a19 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -30,12 +30,12 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <halt.h> -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif /* Stumpy USB Reset Disable defined in cmos.layout */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include "option_table.h" #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) #else @@ -52,7 +52,7 @@ void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(DRIVERS_UART_8250IO) /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/scaleway/tagada/bootblock.c b/src/mainboard/scaleway/tagada/bootblock.c index b926275302..b03583c4a2 100644 --- a/src/mainboard/scaleway/tagada/bootblock.c +++ b/src/mainboard/scaleway/tagada/bootblock.c @@ -24,6 +24,6 @@ void bootblock_mainboard_init(void) { - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_SPEW, "Board Serial: %s.\n", bmcinfo_serial()); } diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 1f87378135..2bb985285a 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -23,7 +23,7 @@ #include <device/pci_ids.h> #include <device/path.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <device/mmio.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index ecc2b2779b..169b04dd59 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <arch/interrupt.h> diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 0611a6d959..34c81a2dea 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -30,7 +30,7 @@ void main(void) clock_init(); // re-initialize UART - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) uart_init(CONFIG_UART_FOR_CONSOLE); sdram_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 0a1e816f23..6279d9c060 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index d688cc95de..1d6410dcd6 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 4f1fa4794c..f32312d6dc 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -86,7 +86,7 @@ void get_bus_conf(void) m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index bf3528d714..76d255be60 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -222,7 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 30241a0588..c234d30a48 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -159,7 +159,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_early_setup(); sb7xx_51xx_early_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 1cefda9285..f589ef6c8d 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 084fc487fb..73951d18e2 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index 4cfee2e9e0..e7d65a0325 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <console/console.h> -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) #include <arch/interrupt.h> #include <x86emu/x86emu.h> @@ -96,7 +96,7 @@ static void mainboard_enable(struct device *dev) { (void)dev; -#if IS_ENABLED(CONFIG_VGA_ROM_RUN) +#if CONFIG(VGA_ROM_RUN) printk(BIOS_DEBUG, "Installing INT15 handler...\n"); mainboard_interrupt_handlers(0x15, &vx900_int15_handler); #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 29f42745ce..c31cb70bb0 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -424,7 +424,7 @@ static void set_resource(struct device *dev, struct resource *resource, } -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -438,7 +438,7 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9da4e8ee59..381d19843e 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -410,7 +410,7 @@ static void set_resource(struct device *dev, struct resource *resource, report_resource_stored(dev, resource, buf); } -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) extern struct device *vga_pri; // the primary vga device, defined in device.c #endif @@ -424,7 +424,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) +#if CONFIG(CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7a75997963..367fecafa5 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -367,7 +367,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index ddfab82e78..44f49ea094 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -366,7 +366,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 9840c1c73c..fea097f6c6 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -32,7 +32,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { AGESA_STATUS status; - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + if (CONFIG(ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); if (status == AGESA_SUCCESS) Post->MemConfig.MemRestoreCtl = 1; diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 43b205a14d..93625fce12 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -20,7 +20,7 @@ #include <AGESA.h> #include <AMD.h> -#define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER) /* eventlog */ const char *agesa_struct_name(int state); @@ -30,7 +30,7 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); /* For suspend-to-ram support. */ -#if !IS_ENABLED(CONFIG_CPU_AMD_PI) +#if !CONFIG(CPU_AMD_PI) /* TODO: With binaryPI we need different interface. */ AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock); AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock); @@ -89,18 +89,18 @@ void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); -#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) +#if CONFIG(CPU_AMD_PI_00660F01) typedef void AMD_S3SAVE_PARAMS; #endif void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ #define HAS_AGESA_FCH_OEM_CALLOUT \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) + CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ + CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) || \ + CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #if HAS_AGESA_FCH_OEM_CALLOUT /* FIXME: Structures included here were supposed to be private to AGESA. */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 405a7009bc..5090352e9a 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -22,7 +22,7 @@ void print_debug_addr(const char *str, void *val) { -#if IS_ENABLED(CONFIG_DEBUG_CAR) +#if CONFIG(DEBUG_CAR) printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } @@ -206,7 +206,7 @@ void dump_pci_devices_on_bus(u32 busn) } } -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl) { int i; @@ -300,17 +300,17 @@ void dump_io_resources(u32 port) } } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void print_tx(const char *strval, u32 val) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } void print_t(const char *strval) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s", strval); #endif } @@ -318,7 +318,7 @@ void print_t(const char *strval) void print_tf(const char *func, const char *strval) { -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s: %s", func, strval); #endif } diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a23303ebfa..3710d15b77 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -32,7 +32,7 @@ void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); void dump_pci_devices(void); void dump_pci_devices_on_bus(u32 busn); -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); #endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index afa07bb4d3..d8784ac728 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -22,7 +22,7 @@ // mmconf is not ready yet void set_bsp_node_CHtExtNodeCfgEn(void) { -#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT) +#if CONFIG(EXT_RT_TBL_SUPPORT) u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index f82f238bc0..871a4366c2 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -74,7 +74,7 @@ static void nb_control_init(struct device *dev) enable_c_states = 0; enable_cc6 = 0; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) uint8_t nvram; if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 8323c1e20f..bbaec53887 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -153,7 +153,7 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); -#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) +#if CONFIG(DIMM_DDR3) && !CONFIG(NORTHBRIDGE_AMD_AGESA) uint8_t node; uint8_t slot; uint8_t dimm_present; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index d202cd89bd..16b7becccc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -35,7 +35,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) #include <cpu/amd/multicore.h> #include <pc80/mc146818rtc.h> #endif @@ -49,7 +49,7 @@ #include <cpu/amd/model_10xxx_rev.h> #endif -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #include "../amdmct/mct_ddr3/s3utils.h" #endif @@ -316,7 +316,7 @@ static void amdfam10_scan_chains(struct device *dev) { struct bus *link; -#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) +#if CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA) if (is_fam15h()) { uint8_t current_link_number = 0; @@ -361,7 +361,7 @@ static void amdfam10_scan_chains(struct device *dev) for (link = dev->link_list; link; link = link->next) { if (link->ht_link_up) { - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) amd_g34_fixup(link, dev); amdfam10_scan_chain(link); } @@ -581,7 +581,7 @@ static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -640,7 +640,7 @@ static void mcf0_control_init(struct device *dev) { } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *amdfam10_northbridge_acpi_name(const struct device *dev) { return ""; @@ -653,7 +653,7 @@ static struct device_operations northbridge_operations = { .enable_resources = pci_dev_enable_resources, .init = mcf0_control_init, .scan_bus = amdfam10_scan_chains, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = northbridge_acpi_write_vars, .acpi_name = amdfam10_northbridge_acpi_name, @@ -886,7 +886,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) uint32_t topmem = (uint32_t) bsp_topmem(); uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ @@ -985,7 +985,7 @@ static void amdfam10_domain_set_resources(struct device *dev) i, mmio_basek, basek, limitk); } -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif @@ -1035,7 +1035,7 @@ static void amdfam10_domain_scan_bus(struct device *dev) } } -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int amdfam10_get_smbios_data16(int *count, int handle, unsigned long *current) { @@ -1085,7 +1085,7 @@ static int amdfam10_get_smbios_data16(int *count, int handle, static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) { if (is_fam15h()) { - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { switch (speed) { case 0x4: return 333; @@ -1106,7 +1106,7 @@ static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) return 0; } } else { - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + if (CONFIG(DIMM_DDR2)) { switch (speed) { case 1: return 200; @@ -1121,7 +1121,7 @@ static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) default: return 0; } - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + } else if (CONFIG(DIMM_DDR3)) { switch (speed) { case 3: return 333; @@ -1185,7 +1185,7 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, cols = mem_info->dct_stat[node].DimmCols[slot]; ranks = mem_info->dct_stat[node].DimmRanks[slot]; banks = mem_info->dct_stat[node].DimmBanks[slot]; -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) chip_size = mem_info->dct_stat[node].DimmChipSize[slot]; chip_width = mem_info->dct_stat[node].DimmChipWidth[slot]; #else @@ -1193,7 +1193,7 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, chip_width = 0; #endif uint64_t dimm_size_bytes; - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { width = mem_info->dct_stat[node].DimmWidth[slot]; dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8; } else { @@ -1226,9 +1226,9 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); } t->device_locator = smbios_add_string(t->eos, string_buffer); - if (IS_ENABLED(CONFIG_DIMM_DDR2)) + if (CONFIG(DIMM_DDR2)) t->memory_type = MEMORY_TYPE_DDR2; - else if (IS_ENABLED(CONFIG_DIMM_DDR3)) + else if (CONFIG(DIMM_DDR3)) t->memory_type = MEMORY_TYPE_DDR3; t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; if (mem_info->dct_stat[node].DimmRegistered[slot]) @@ -1245,13 +1245,13 @@ static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); t->serial_number = smbios_add_string(t->eos, string_buffer); } - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + if (CONFIG(DIMM_DDR2)) { /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */ t->minimum_voltage = 1800; t->maximum_voltage = 1800; t->configured_voltage = 1800; - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { -#if IS_ENABLED(CONFIG_DIMM_DDR3) + } else if (CONFIG(DIMM_DDR3)) { +#if CONFIG(DIMM_DDR3) /* Find the maximum and minimum supported voltages */ uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot]; uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot]; @@ -1308,7 +1308,7 @@ static int amdfam10_get_smbios_data(struct device *dev, int *handle, unsigned lo } #endif -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *amdfam10_domain_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -1324,10 +1324,10 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = amdfam10_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = amdfam10_domain_acpi_name, #endif -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = amdfam10_get_smbios_data, #endif }; @@ -1356,7 +1356,7 @@ static void sysconf_init(struct device *dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if CONFIG(ENABLE_APIC_EXT_ID) if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; @@ -1451,7 +1451,7 @@ static void cpu_bus_scan(struct device *dev) } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif @@ -1656,7 +1656,7 @@ static void cpu_bus_scan(struct device *dev) } } -#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; @@ -1978,7 +1978,7 @@ static void root_complex_enable_dev(struct device *dev) } static void root_complex_finalize(void *chip_info) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(HAVE_ACPI_RESUME) && CONFIG(DIMM_DDR3) save_mct_information_to_nvram(); #endif } diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 8dee9ab814..4f31a5e848 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -150,8 +150,8 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi uint8_t MaxDimmsInstallable = 2; /* Return limited maximum RAM frequency */ - if (IS_ENABLED(CONFIG_DIMM_DDR2)) { - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_DDR2)) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 53 */ if (count > 2) { /* Limit to DDR2-533 */ @@ -170,7 +170,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi } } } - } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + } else if (CONFIG(DIMM_DDR3)) { if (voltage == 0) { printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); voltage = 0x1; @@ -179,7 +179,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi if (is_fam15h()) { if (CONFIG_CPU_SOCKET_TYPE == 0x15) { /* Socket G34 */ - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* Fam15h BKDG Rev. 3.14 Table 27 */ if (voltage & 0x4) { /* 1.25V */ @@ -317,7 +317,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi } } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { /* Socket C32 */ - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* Fam15h BKDG Rev. 3.14 Table 30 */ if (voltage & 0x4) { /* 1.25V */ @@ -486,7 +486,7 @@ uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t regi */ } } else { - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + if (CONFIG(DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 34 */ if (count > 2) { /* Limit to DDR3-800 */ @@ -548,7 +548,7 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) } -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) u8 mctGetProcessorPackageType(void) { /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ u32 BrandId = cpuid_ebx(0x80000001); @@ -601,7 +601,7 @@ void amdmct_cbmem_store_info(struct sys_info *sysinfo) mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); /* Zero out invalid/unused pointers */ -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) for (i = 0; i < MAX_NODES_SUPPORTED; i++) { mem_info->dct_stat[i].C_MCTPtr = NULL; mem_info->dct_stat[i].C_DCTPtr[0] = NULL; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index f919335360..8c33ad8156 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1489,13 +1489,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8) +#if CONFIG(LIMIT_HT_DOWN_WIDTH_8) cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8) +#if CONFIG(LIMIT_HT_UP_WIDTH_8) cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 6552be9532..bad8993395 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -272,7 +272,7 @@ void amd_ht_init(struct sys_info *sysinfo) */ void amd_ht_fixup(struct sys_info *sysinfo) { printk(BIOS_DEBUG, "%s\n", __func__); - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) { + if (CONFIG(CPU_AMD_MODEL_10XXX)) { uint8_t rev_gte_d = 0; uint8_t fam15h = 0; uint8_t dual_node = 0; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6f09b12a8a..9178c782d4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2620,7 +2620,7 @@ restartinit: mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -2692,11 +2692,11 @@ restartinit: nvram = 0; set_option("allow_spd_nvram_cache_restore", &nvram); -#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT) +#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif - if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) { + if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) { /* Assume 1.5V operation */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; @@ -3674,7 +3674,7 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); if (restore_mct_information_from_nvram(1) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -5836,7 +5836,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { @@ -5853,7 +5853,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) allow_config_restore = 0; #else diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 7267f12000..a78a752052 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -536,7 +536,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); for (i = 0; i < 12; i++) @@ -654,7 +654,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); for (i = 0; i < 12; i++) @@ -1093,7 +1093,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste } /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (node = 0; node < MAX_NODES_SUPPORTED; node++) { for (channel = 0; channel < 2; channel++) { struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index db92fa789e..92dc0b853c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -56,7 +56,7 @@ UPDATE AS NEEDED #endif #ifndef MAX_DIMMS_SUPPORTED -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MAX_DIMMS_SUPPORTED 6 #else #define MAX_DIMMS_SUPPORTED 8 @@ -72,7 +72,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 @@ -112,13 +112,13 @@ UPDATE AS NEEDED static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) #include <northbridge/amd/amdmct/mct_ddr3/mct_d.h> #else #include <northbridge/amd/amdmct/mct/mct_d.h> #endif -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void); void mctGetDQSSigTmg_D(void); u8 mctSetNodeBoundary_D(void); @@ -144,7 +144,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc void mctHookAfterAnyTraining(void); uint64_t mctGetLogicalCPUID_D(u8 node); -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat); void vErratum414(struct DCTStatStruc *pDCTstat); u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b7d24764ed..e42085dce5 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -102,9 +102,9 @@ u16 mctGet_NVbits(u8 index) if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) { int limit = val; - if (IS_ENABLED(CONFIG_DIMM_DDR3)) + if (CONFIG(DIMM_DDR3)) limit = ddr3_limits[nvram & 0xf]; - else if (IS_ENABLED(CONFIG_DIMM_DDR2)) + else if (CONFIG(DIMM_DDR2)) limit = ddr2_limits[nvram & 0x3]; val = min(limit, val); } @@ -130,16 +130,16 @@ u16 mctGet_NVbits(u8 index) //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 4; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 7; #endif break; case NV_RDWRQBYP: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 2; -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 3; #endif break; @@ -193,9 +193,9 @@ u16 mctGet_NVbits(u8 index) val = !!nvram; break; case NV_BurstLen32: -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = 0; /* 64 byte mode */ -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) val = 1; /* 32 byte mode */ #endif break; @@ -214,9 +214,9 @@ u16 mctGet_NVbits(u8 index) case NV_BottomIO: case NV_BottomUMA: /* address bits [31:24] */ -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) val = (CONFIG_MMCONF_BASE_ADDRESS >> 24); -#elif IS_ENABLED(CONFIG_GFXUMA) +#elif CONFIG(GFXUMA) #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G)) #error "MMCONF_BASE_ADDRESS is too small" #endif @@ -360,12 +360,12 @@ void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) if (pDCTstat->DimmRegistered[i + 1]) ch2_registered = 1; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) { + if (CONFIG(DEBUG_RAM_SETUP)) { printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count); printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; @@ -421,7 +421,7 @@ void mctHookAfterCPU(void) } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) void mctSaveDQSSigTmg_D(void) { } @@ -470,7 +470,7 @@ void mctHookAfterDramInit(void) { } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -504,7 +504,7 @@ void vErratum414(struct DCTStatStruc *pDCTstat) void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -513,7 +513,7 @@ void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc #endif } -#if IS_ENABLED(CONFIG_DIMM_DDR3) +#if CONFIG(DIMM_DDR3) u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { @@ -534,7 +534,7 @@ uint64_t mctGetLogicalCPUID_D(u8 node) return mctGetLogicalCPUID(node); } -#if IS_ENABLED(CONFIG_DIMM_DDR2) +#if CONFIG(DIMM_DDR2) u8 mctSetNodeBoundary_D(void) { return 0; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index c24fb2d1b2..3f86427a8e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -36,7 +36,7 @@ #include <assert.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -370,7 +370,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -611,7 +611,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 19fb81415e..bf7c59adfd 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -35,7 +35,7 @@ #include <arch/acpigen.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -355,7 +355,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -610,7 +610,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) AGESAWRAPPER(amdinitmid); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9bbb2debc2..eb38c428f5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -37,7 +37,7 @@ #include <arch/acpigen.h> #include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #endif @@ -371,7 +371,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) +#if CONFIG(MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -843,7 +843,7 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) AGESAWRAPPER(amdinitmid); diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index b05c12012e..28f2876e95 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -55,8 +55,8 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)) + AmdResetParams.FchInterface.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) AmdResetParams.FchInterface.Xhci1Enable = TRUE; AmdResetParams.FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); @@ -96,7 +96,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) * init_timer() needs to be called on CZ PI, because AGESA resets the LAPIC reload value * on the AMD_INIT_EARLY call */ - if (IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01)) + if (CONFIG(CPU_AMD_PI_00660F01)) init_timer(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); @@ -299,7 +299,7 @@ const void *agesawrapper_locate_module (const CHAR8 name[8]) const AMD_MODULE_HEADER* module; size_t file_size; - if (IS_ENABLED(CONFIG_VBOOT)) { + if (CONFIG(VBOOT)) { /* Use phys. location in flash and prevent vboot from searching cbmem */ agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; file_size = 0x100000; diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index e5971d845f..e1cec43c32 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -16,7 +16,7 @@ #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <stdint.h> #include <Porting.h> @@ -51,7 +51,7 @@ static inline int agesawrapper_amds3laterestore(void) { return -1; } #endif -#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) +#if CONFIG(BINARYPI_LEGACY_WRAPPER) const void *agesawrapper_locate_module (const CHAR8 name[8]); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index fcf347c54f..3bb1f67b59 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -54,7 +54,7 @@ Definitions: // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 79775757b5..ec36c06c16 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -97,7 +97,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) +#if CONFIG(ENABLE_FSP_FAST_BOOT) UpdData->PcdFastboot = UPD_ENABLE; #endif /* diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4a5ebbd0a0..648aa48fef 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -190,7 +190,7 @@ static void gma_func0_init(struct device *dev) mmio = res2mmio(gtt_res, 0, 0); - if (!IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); pci_dev_init(dev); @@ -205,7 +205,7 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index e9d35207c7..0f0d38339e 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3b043a3b96..0fd0228268 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -35,7 +35,7 @@ #include "chip.h" #include "haswell.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -240,7 +240,7 @@ static void power_well_enable(void) * after we power up the AUX channel until we can talk to it. * So get that going right now. We can't turn on the panel, yet, just VDD. */ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); } } @@ -475,7 +475,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ac0b84f1d0..ad4563bb35 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -395,7 +395,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index bf88418203..91959c7cd8 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -31,7 +31,7 @@ */ /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(NB) #else @@ -297,7 +297,7 @@ static const u8 register_values[] = { * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ -#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM) +#if CONFIG(SDRAMPWR_4DIMM) SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ #else SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */ @@ -460,7 +460,7 @@ static void set_dram_buffer_strength(void) } } - if (IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)) { + if (CONFIG(SDRAMPWR_4DIMM)) { /* * For a 4 DIMM board, based on ASUS P2B-LS mainboard. * diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index e20d559fa4..4711359181 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -29,7 +29,7 @@ void sdram_enable(void); void sdram_initialize(void); /* Debug */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void dump_spd_registers(void); void dump_pci_device(unsigned dev); #else diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1913b524a5..7ab252585a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -93,7 +93,7 @@ static void i945m_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -143,7 +143,7 @@ static void i945_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -237,7 +237,7 @@ static void i945_setup_egress_port(void) /* Egress Port Virtual Channel 1 Configuration */ reg32 = EPBAR32(0x2c); reg32 &= 0xffffff00; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) reg32 |= 0x1a; /* 1067MHz */ } @@ -256,7 +256,7 @@ static void i945_setup_egress_port(void) reg32 |= (0x0a << 16); EPBAR32(EPVC1RCAP) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ EPBAR32(EPVC1IST + 0) = 0x01380138; EPBAR32(EPVC1IST + 4) = 0x01380138; @@ -941,14 +941,14 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 26b6c84352..633b09d31b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -236,9 +236,9 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / (pixel_n + 2) / (pixel_p1 * pixel_p2)); - printk(BIOS_INFO, "VGA mode: %s\n", IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? + printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ? "Linear framebuffer" : "text"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { /* Disable panel fitter (we're in native resolution). */ write32(mmiobase + PF_CTL(0), 0); write32(mmiobase + PF_WIN_SZ(0), 0); @@ -301,7 +301,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); } else { @@ -380,7 +380,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, else printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); @@ -660,7 +660,7 @@ static void gma_ngi(struct device *const dev) int err; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) panel_setup(mmiobase, dev); /* probe if VGA is connected and always run */ @@ -704,7 +704,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { if (acpi_is_wakeup_s3()) { printk(BIOS_INFO, "Skipping native VGA initialization when resuming from ACPI S3.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a9bfde7805..a93cf1e718 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -33,7 +33,7 @@ #include <timestamp.h> /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -96,7 +96,7 @@ static void ram_read32(u32 offset) read32((void *)offset); } -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -112,7 +112,7 @@ void sdram_dump_mchbar_registers(void) static int memclk(void) { - int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; @@ -127,7 +127,7 @@ static int memclk(void) static u16 fsbclk(void) { - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 400; case 1: return 533; @@ -137,7 +137,7 @@ static u16 fsbclk(void) MCHBAR32(CLKCFG) & 7); } return 0xffff; - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 1066; case 1: return 533; @@ -386,7 +386,7 @@ static void gather_common_timing(struct sys_info *sysinfo, bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0) + if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0) hexdump(raw_spd, bytes_read); if (bytes_read != 64) { /* Try again with SMBUS byte read */ @@ -394,7 +394,7 @@ static void gather_common_timing(struct sys_info *sysinfo, " trying smbus byte operation.\n"); for (j = 0; j < 64; j++) raw_spd[j] = spd_read_byte(device, j); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) hexdump(raw_spd, 64); } @@ -404,7 +404,7 @@ static void gather_common_timing(struct sys_info *sysinfo, continue; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&dimm_info); if (dimm_info.flags.is_ecc) @@ -841,7 +841,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index) return nc; } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -896,7 +896,7 @@ static const u8 single_channel_strength_multiplier[] = { 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -1027,7 +1027,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); /* We drive both channels with the same speed */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x26262626; break; @@ -1036,7 +1036,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) case 667: channeldll = 0x11111111; break; } - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x33333333; break; @@ -1052,7 +1052,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } @@ -1769,7 +1769,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) { u32 clkcfg; u8 reg8; - u8 offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; printk(BIOS_DEBUG, "Setting Memory Frequency... "); @@ -1854,7 +1854,7 @@ static void sdram_program_clock_crossing(void) /** * We add the indices according to our clocks from CLKCFG. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1899,7 +1899,7 @@ static void sdram_program_clock_crossing(void) 0xffffffff, 0xffffffff, /* nonexistent */ }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ @@ -2119,7 +2119,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo) if (sysinfo->interleaved) { reg32 = MCHBAR32(DCC); -#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION) +#if CONFIG(CHANNEL_XOR_RANDOMIZATION) reg32 &= ~(1 << 10); reg32 |= (1 << 9); #else @@ -2175,7 +2175,7 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { if (i945_silicon_revision() > 1) { /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ u16 peg_bits = (1 << 5) | (1 << 0); @@ -2493,9 +2493,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) { u8 clocks[2] = { 0, 0 }; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) #define CLOCKS_WIDTH 2 -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) @@ -2510,7 +2510,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; -#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE) +#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals * to unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock @@ -2755,7 +2755,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) sdram_program_graphics_frequency(&sysinfo); else pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 98bdc02afd..2d1eee6947 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -70,7 +70,7 @@ void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); void udelay(u32 us); -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void); #endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index 664022bf0f..df8aad7c62 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 2c958a4c86..a5cac7b19a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -73,7 +73,7 @@ static void nehalem_setup_bars(void) pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -82,7 +82,7 @@ static void nehalem_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index be17e2fa12..86fc583f88 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -603,7 +603,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 6906714457..8a4f64c809 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -78,7 +78,7 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); @@ -90,7 +90,7 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = northbridge_acpi_name, #endif }; diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 73a82407fe..8bacc77598 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -268,7 +268,7 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); } else { diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 4cdb27a898..5aea59ef17 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -28,7 +28,7 @@ #include <string.h> /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -134,7 +134,7 @@ static int decode_spd(struct dimminfo *d, int i) d->tRCD = d->spd_data[29]; d->tWR = d->spd_data[36]; d->ranks = d->sides; // XXX -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) const char *ubso[2] = { "UB", "SO" }; #endif PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i); @@ -311,7 +311,7 @@ static void sdram_read_spds(struct sysinfo *s) } } -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) static u32 fsb_reg_to_mhz(u32 speed) { return (speed * 133) + 667; diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 73692037c3..dce9f67029 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -35,7 +35,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 44eebf3215..ad579c6fc3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -59,7 +59,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -68,7 +68,7 @@ static void sandybridge_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) @@ -159,7 +159,7 @@ static void start_peg_link_training(void) * As the MRC has its own initialization code skip it. */ if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & BASE_REV_MASK) != BASE_REV_IVB) || - IS_ENABLED(CONFIG_HAVE_MRC)) + CONFIG(HAVE_MRC)) return; deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index ce2abd9d88..00180fe4f0 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -625,7 +625,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); @@ -636,7 +636,7 @@ static void gma_func0_init(struct device *dev) /* Running graphics init on S3 breaks Linux drm driver. */ if (!acpi_is_wakeup_s3() && - IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ab0554c7df..e58a0ebc3a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -98,7 +98,7 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 53fb4d3530..16bc314b90 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -28,7 +28,7 @@ static void pcie_disable(struct device *dev) dev->enabled = 0; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { assert(dev); @@ -90,7 +90,7 @@ static struct device_operations device_ops = { .disable = pcie_disable, .init = pci_dev_init, .ops_pci = &pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, #endif }; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index caba76efac..3f62d10a1c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -210,7 +210,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", dimm->dimm[channel][slot].dimms_per_channel, dimms_on_channel); - if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) + if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); else spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6bda9ed3dd..fda662f4f6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -390,7 +390,7 @@ unsigned int get_mem_min_tck(void) /* If this is zero, it just means devicetree.cb didn't set it */ if (!cfg || cfg->max_mem_clock_mhz == 0) { - if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ; rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 853fdb83d0..852da7aa26 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -41,7 +41,7 @@ * MRC scrambler seed offsets should be reserved in * mainboard cmos.layout and not covered by checksum. */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include "option_table.h" #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) @@ -241,7 +241,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* mrc.bin reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); /* For reference print the System Agent version diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 9cb3df3565..5ccc77e9be 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7e91cc5f5d..8de568a0ea 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -36,9 +36,9 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) #include <southbridge/intel/i82801jx/nvs.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/nvs.h> #endif @@ -71,7 +71,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index ea00f293e1..72ef1a915e 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -25,7 +25,7 @@ #include <halt.h> #include <lib.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ @@ -174,7 +174,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, return CB_ERR; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&decoded_dimm); if (!(decoded_dimm.width & (0x08 | 0x10))) { @@ -383,7 +383,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK) return CB_ERR; - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr3(&decoded_dimm); /* x4 DIMMs are not supported (true for both ddr2 and ddr3) */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index d14809e827..f172623108 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> #else #include <southbridge/intel/i82801jx/i82801jx.h> diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 209601d951..41ea1545cf 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -244,7 +244,7 @@ static const struct pci_driver lpc_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX900_LPC, }; -#if IS_ENABLED(CONFIG_PIRQ_ROUTE) +#if CONFIG(PIRQ_ROUTE) void pirq_assign_irqs(const u8 *pirq) { struct device *lpc; diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 18ab288dcc..ba4dbc111a 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -52,10 +52,10 @@ static struct tcpa_table *tcpa_log_init(void) /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ if (!cbmem_possibly_online() && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) + !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) return (struct tcpa_table *)_vboot2_tpm_log; else if (ENV_ROMSTAGE && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { + !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { tclt = tcpa_cbmem_init(); if (!tclt) return (struct tcpa_table *)_vboot2_tpm_log; @@ -136,7 +136,7 @@ void tcpa_preram_log_clear(void) tclt->num_entries = 0; } -#if !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) +#if !CONFIG(VBOOT_RETURN_FROM_VERSTAGE) static void recover_tcpa_log(int is_recovery) { struct tcpa_table *preram_log = (struct tcpa_table *)_vboot2_tpm_log; diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index f1b72fbff3..aa2dc09bfc 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -22,12 +22,12 @@ #include <security/tpm/tss.h> #include <stdlib.h> #include <string.h> -#if IS_ENABLED(CONFIG_VBOOT) +#if CONFIG(VBOOT) #include <vb2_api.h> #include <assert.h> #endif -#if IS_ENABLED(CONFIG_TPM1) +#if CONFIG(TPM1) static uint32_t tpm1_invoke_state_machine(void) { uint8_t disabled; @@ -51,7 +51,7 @@ static uint32_t tpm1_invoke_state_machine(void) } } - if (!!deactivated != IS_ENABLED(CONFIG_TPM_DEACTIVATE)) { + if (!!deactivated != CONFIG(TPM_DEACTIVATE)) { printk(BIOS_INFO, "TPM: Unexpected TPM deactivated state. Toggling...\n"); result = tlcl_set_deactivated(!deactivated); @@ -167,7 +167,7 @@ uint32_t tpm_setup(int s3flag) } } -#if IS_ENABLED(CONFIG_TPM1) +#if CONFIG(TPM1) result = tpm1_invoke_state_machine(); #endif @@ -185,7 +185,7 @@ uint32_t tpm_clear_and_reenable(void) return result; } -#if IS_ENABLED(CONFIG_TPM1) +#if CONFIG(TPM1) result = tlcl_set_enable(); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Can't set enabled state.\n"); @@ -214,14 +214,14 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, if (result != TPM_SUCCESS) return result; - if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT)) + if (CONFIG(VBOOT_MEASURED_BOOT)) tcpa_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); return TPM_SUCCESS; } -#if IS_ENABLED(CONFIG_VBOOT) +#if CONFIG(VBOOT) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -239,7 +239,7 @@ uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, printk(BIOS_ERR, "TPM: Can't initialize library.\n"); return result; } - if (IS_ENABLED(CONFIG_TPM1)) { + if (CONFIG(TPM1)) { hash_alg = VB2_HASH_SHA1; } else { /* CONFIG_TPM2 */ hash_alg = VB2_HASH_SHA256; diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c4f2608603..807cb46a3e 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -19,7 +19,7 @@ #include <security/tpm/tss_errors.h> #include <security/tpm/tss/vendor/cr50/cr50.h> -#if IS_ENABLED(CONFIG_TPM1) +#if CONFIG(TPM1) #include <security/tpm/tss/tcg-1.2/tss_structures.h> @@ -53,7 +53,7 @@ uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags); #endif -#if IS_ENABLED(CONFIG_TPM2) +#if CONFIG(TPM2) #include <security/tpm/tss/tcg-2.0/tss_structures.h> diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 59eaf2f540..fb1fc461b8 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -36,7 +36,7 @@ static int vb2_get_recovery_reason_shared_data(void) void vb2_save_recovery_reason_vbnv(void) { - if (!IS_ENABLED(CONFIG_VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) + if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) return; int reason = vb2_get_recovery_reason_shared_data(); @@ -48,7 +48,7 @@ void vb2_save_recovery_reason_vbnv(void) static void vb2_clear_recovery_reason_vbnv(void *unused) { - if (!IS_ENABLED(CONFIG_VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) + if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) return; set_recovery_mode_into_vbnv(0); @@ -73,13 +73,13 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, */ static int vboot_possibly_executed(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) { - if (ENV_BOOTBLOCK && IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + if (ENV_BOOTBLOCK && CONFIG(VBOOT_SEPARATE_VERSTAGE)) return 0; return 1; } - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { if (ENV_BOOTBLOCK) return 0; return 1; @@ -169,7 +169,7 @@ int vboot_developer_mode_enabled(void) return 0; } -#if IS_ENABLED(CONFIG_VBOOT_NO_BOARD_SUPPORT) +#if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. * get_recovery_mode_switch should be implemented as default function. diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index da4e1ca09f..59c830f1bc 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -44,7 +44,7 @@ static const size_t vb_work_buf_size = 16 * KiB; static struct vb2_working_data * const vboot_get_working_data(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) /* cbmem_add() does a cbmem_find() first. */ return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); else @@ -53,7 +53,7 @@ static struct vb2_working_data * const vboot_get_working_data(void) static size_t vb2_working_data_size(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) return vb_work_buf_size; else return REGION_SIZE(vboot2_work); @@ -171,7 +171,7 @@ void vb2_store_selected_region(void) * Therefore, the selected region contents would not be initialized * so don't automatically add results when cbmem comes online. */ -#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) +#if !CONFIG(VBOOT_STARTS_IN_ROMSTAGE) static void vb2_store_selected_region_cbmem(int unused) { vb2_store_selected_region(); diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 1ace632aff..39cd6141fd 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -167,7 +167,7 @@ static const uint8_t secdata_kernel[] = { */ static const uint8_t rec_hash_data[REC_HASH_NV_SIZE] = { }; -#if IS_ENABLED(CONFIG_TPM2) +#if CONFIG(TPM2) /* * Different sets of NVRAM space attributes apply to the "ro" spaces, * i.e. those which should not be possible to delete or modify once @@ -264,7 +264,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) */ RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); - if (IS_ENABLED(CONFIG_VBOOT_HAS_REC_HASH_SPACE)) + if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); RETURN_ON_FAILURE(set_firmware_space(ctx->secdata)); @@ -385,7 +385,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) VB2_SECDATA_SIZE)); /* Define and set rec hash space, if available. */ - if (IS_ENABLED(CONFIG_VBOOT_HAS_REC_HASH_SPACE)) + if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); return TPM_SUCCESS; @@ -481,7 +481,7 @@ uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) { - if (IS_ENABLED(CONFIG_CR50_IMMEDIATELY_COMMIT_FW_SECDATA)) + if (CONFIG(CR50_IMMEDIATELY_COMMIT_FW_SECDATA)) tlcl_cr50_enable_nvcommits(); return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE); } diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 636e5e3806..b99941875c 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -91,11 +91,11 @@ void regen_vbnv_crc(uint8_t *vbnv_copy) */ void read_vbnv(uint8_t *vbnv_copy) { - if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + if (CONFIG(VBOOT_VBNV_CMOS)) read_vbnv_cmos(vbnv_copy); - else if (IS_ENABLED(CONFIG_VBOOT_VBNV_EC)) + else if (CONFIG(VBOOT_VBNV_EC)) read_vbnv_ec(vbnv_copy); - else if (IS_ENABLED(CONFIG_VBOOT_VBNV_FLASH)) + else if (CONFIG(VBOOT_VBNV_FLASH)) read_vbnv_flash(vbnv_copy); /* Check data for consistency */ @@ -109,11 +109,11 @@ void read_vbnv(uint8_t *vbnv_copy) */ void save_vbnv(const uint8_t *vbnv_copy) { - if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + if (CONFIG(VBOOT_VBNV_CMOS)) save_vbnv_cmos(vbnv_copy); - else if (IS_ENABLED(CONFIG_VBOOT_VBNV_EC)) + else if (CONFIG(VBOOT_VBNV_EC)) save_vbnv_ec(vbnv_copy); - else if (IS_ENABLED(CONFIG_VBOOT_VBNV_FLASH)) + else if (CONFIG(VBOOT_VBNV_FLASH)) save_vbnv_flash(vbnv_copy); /* Clear initialized flag to force cached data to be updated */ @@ -156,7 +156,7 @@ int vbnv_udc_enable_flag(void) void vbnv_init(uint8_t *vbnv_copy) { - if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + if (CONFIG(VBOOT_VBNV_CMOS)) vbnv_init_cmos(vbnv_copy); read_vbnv(vbnv_copy); } diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index 9c801d84fe..7758ef6198 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -39,7 +39,7 @@ static void clear_vbnv_battery_cutoff_flag(uint8_t *vbnv_copy) /* Return non-zero if backup was used. */ static int restore_from_backup(uint8_t *vbnv_copy) { - if (!IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH)) + if (!CONFIG(VBOOT_VBNV_CMOS_BACKUP_TO_FLASH)) return 0; printk(BIOS_INFO, "VBNV: CMOS invalid, restoring from flash\n"); @@ -99,7 +99,7 @@ void vbnv_init_cmos(uint8_t *vbnv_copy) } } -#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) +#if CONFIG(VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) static void back_up_vbnv_cmos(void *unused) { uint8_t vbnv_cmos[VBOOT_VBNV_BLOCK_SIZE]; diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index c80650f3be..51bc682893 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -60,7 +60,7 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) * pre-ram stage, then bail out early. */ if (ENV_BOOTBLOCK || - (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))) + (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))) return -1; struct vboot_handoff *vboot_handoff; @@ -124,7 +124,7 @@ void __weak vboot_platform_prepare_reboot(void) void vboot_reboot(void) { - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + if (CONFIG(CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); vboot_platform_prepare_reboot(); board_reset(); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 61f5931fe5..8c92437a3c 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -104,7 +104,7 @@ void verstage_main(void); void verstage_mainboard_init(void); /* Check boot modes */ -#if IS_ENABLED(CONFIG_VBOOT) +#if CONFIG(VBOOT) int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); int vboot_recovery_mode_memory_retrain(void); diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index 4e69b7cddd..6aa5103f60 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -88,7 +88,7 @@ uint32_t vboot_init_crtm(void) } } - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { struct cbfsf romstage_data; /* measure romstage from RO */ if (cbfs_boot_locate(&romstage_data, @@ -111,7 +111,7 @@ uint32_t vboot_init_crtm(void) } } - if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) { struct cbfsf verstage_data; /* measure verstage from RO */ if (cbfs_boot_locate(&verstage_data, diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 84ee9e63b5..e1799b8e84 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -46,7 +46,7 @@ */ uint32_t vboot_init_crtm(void); -#if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && \ +#if (CONFIG(VBOOT_MEASURED_BOOT) && \ !ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && !ENV_SMM) /* * Measures cbfs data via hook (cbfs) diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index e8464140b9..2bb26a8974 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -79,18 +79,18 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } /* TODO: Set these in depthcharge */ - if (!IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH)) + if (!CONFIG(VBOOT_PHYSICAL_DEV_SWITCH)) vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; - if (IS_ENABLED(CONFIG_VBOOT_EC_SOFTWARE_SYNC)) { + if (CONFIG(VBOOT_EC_SOFTWARE_SYNC)) { vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC; - if (IS_ENABLED(CONFIG_VBOOT_EC_SLOW_UPDATE)) + if (CONFIG(VBOOT_EC_SLOW_UPDATE)) vb_sd->flags |= VBSD_EC_SLOW_UPDATE; - if (IS_ENABLED(CONFIG_VBOOT_EC_EFS)) + if (CONFIG(VBOOT_EC_EFS)) vb_sd->flags |= VBSD_EC_EFS; } - if (!IS_ENABLED(CONFIG_VBOOT_PHYSICAL_REC_SWITCH)) + if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH)) vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; - if (IS_ENABLED(CONFIG_VBOOT_OPROM_MATTERS)) { + if (CONFIG(VBOOT_OPROM_MATTERS)) { vb_sd->flags |= VBSD_OPROM_MATTERS; /* * Inform vboot if the display was enabled by dev/rec @@ -179,7 +179,7 @@ void vboot_fill_handoff(void) * Therefore, the vboot results would not be initialized so don't * automatically add results when cbmem comes online. */ -#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) +#if !CONFIG(VBOOT_STARTS_IN_ROMSTAGE) static void vb2_fill_handoff_cbmem(int unused) { vboot_fill_handoff(); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 75f75b5cf8..b6c216d5fa 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -24,14 +24,14 @@ #include <security/vboot/vboot_common.h> /* Ensure vboot configuration is valid: */ -_Static_assert(IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) + - IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) == 1, +_Static_assert(CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) + + CONFIG(VBOOT_STARTS_IN_ROMSTAGE) == 1, "vboot must either start in bootblock or romstage (not both!)"); -_Static_assert(!IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) || - IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK), +_Static_assert(!CONFIG(VBOOT_SEPARATE_VERSTAGE) || + CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "stand-alone verstage must start in (i.e. after) bootblock"); -_Static_assert(!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) || - IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE), +_Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || + CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); /* The stage loading code is compiled and entered from multiple stages. The @@ -40,11 +40,11 @@ _Static_assert(!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) || static int verification_should_run(void) { - if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) return ENV_VERSTAGE; - else if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) return ENV_ROMSTAGE; - else if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return ENV_BOOTBLOCK; else die("impossible!"); @@ -52,7 +52,7 @@ static int verification_should_run(void) static int verstage_should_load(void) { - if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) return ENV_BOOTBLOCK; else return 0; @@ -67,10 +67,10 @@ int vb2_logic_executed(void) if (verstage_should_load() || verification_should_run()) return car_get_var(vboot_executed); - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) { + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { /* All other stages are "after the bootblock" */ return !ENV_BOOTBLOCK; - } else if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { /* Post-RAM stages are "after the romstage" */ #ifdef __PRE_RAM__ return 0; @@ -112,7 +112,7 @@ static void vboot_prepare(void) /* This is not actually possible to hit this condition at * runtime, but this provides a hint to the compiler for dead * code elimination below. */ - if (!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) + if (!CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) return; car_set_var(vboot_executed, 1); @@ -126,7 +126,7 @@ static void vboot_prepare(void) * other platforms the vboot cbmem objects are initialized when * cbmem comes online. */ - if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { + if (ENV_ROMSTAGE && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { vb2_store_selected_region(); vboot_fill_handoff(); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7ab9824843..4aab795871 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -113,14 +113,14 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) * Chrome EC is the only support for vboot_save_hash() & * vboot_retrieve_hash(), if Chrome EC is not enabled then return. */ - if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (!CONFIG(EC_GOOGLE_CHROMEEC)) return 0; /* * Nothing to do since resuming on the platform doesn't require * vboot verification again. */ - if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) + if (!CONFIG(RESUME_PATH_SAME_AS_BOOT)) return 0; /* @@ -128,7 +128,7 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) * RW memory init code is not employed. i.e. memory init code * lives in RO CBFS. */ - if (!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + if (!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return 0; is_resume = vboot_platform_is_resuming(); @@ -306,7 +306,7 @@ void verstage_main(void) * which slot to boot. This is only relevant to vboot if the platform * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ - if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && + if (CONFIG(RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) ctx.flags |= VB2_CONTEXT_S3_RESUME; @@ -318,27 +318,27 @@ void verstage_main(void) timestamp_add_now(TS_END_TPMINIT); /* Enable measured boot mode */ - if (IS_ENABLED(CONFIG_VBOOT_MEASURED_BOOT) && + if (CONFIG(VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { if (vboot_init_crtm() != VB2_SUCCESS) die("Initializing measured boot mode failed!"); } - if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && + if (CONFIG(VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; if (get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; - if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY)) + if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; } - if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && + if (CONFIG(VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE; - if (IS_ENABLED(CONFIG_VBOOT_LID_SWITCH) && !get_lid_switch()) + if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Do early init (set up secdata and NVRAM, load GBB) */ @@ -424,7 +424,7 @@ void verstage_main(void) timestamp_add_now(TS_END_TPMLOCK); /* Lock rec hash space if available. */ - if (IS_ENABLED(CONFIG_VBOOT_HAS_REC_HASH_SPACE)) { + if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) { rv = antirollback_lock_space_rec_hash(); if (rv) { printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", diff --git a/src/security/vboot/verstage.c b/src/security/vboot/verstage.c index afd73f11e0..ef0bd48850 100644 --- a/src/security/vboot/verstage.c +++ b/src/security/vboot/verstage.c @@ -30,7 +30,7 @@ void main(void) exception_init(); verstage_mainboard_init(); - if (IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { + if (CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { verstage_main(); } else { run_romstage(); diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 7937817316..47402b670b 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -60,7 +60,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, .prog = &prog, }; - if (acpi_is_wakeup_s3() && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (acpi_is_wakeup_s3() && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_INFO, "AGESA: Loading stage from cache\n"); // There is no way to tell if this succeeded. stage_cache_load_stage(STAGE_REFCODE, &prog); @@ -71,7 +71,7 @@ static int agesa_locate_stage_file_ramstage(const char *name, if (rmodule_stage_load(&rmod_agesa) < 0) return -1; - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (!CONFIG(NO_STAGE_CACHE)) { printk(BIOS_INFO, "AGESA: Saving stage to cache\n"); stage_cache_add(STAGE_REFCODE, &prog); } @@ -83,14 +83,14 @@ static int agesa_locate_stage_file_ramstage(const char *name, static int agesa_locate_stage_file(const char *name, struct region_device *rdev) { - if (!ENV_RAMSTAGE || !IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + if (!ENV_RAMSTAGE || !CONFIG(AGESA_SPLIT_MEMORY_FILES)) return agesa_locate_stage_file_early(name, rdev); return agesa_locate_stage_file_ramstage(name, rdev); } static const char *get_agesa_cbfs_name(void) { - if (!IS_ENABLED(CONFIG_AGESA_SPLIT_MEMORY_FILES)) + if (!CONFIG(AGESA_SPLIT_MEMORY_FILES)) return CONFIG_AGESA_CBFS_NAME; if (!ENV_RAMSTAGE) return CONFIG_AGESA_PRE_MEMORY_CBFS_NAME; @@ -108,7 +108,7 @@ const void *agesawrapper_locate_module(const char name[8]) fname = get_agesa_cbfs_name(); - if (IS_ENABLED(CONFIG_AGESA_BINARY_PI_AS_STAGE)) + if (CONFIG(AGESA_BINARY_PI_AS_STAGE)) ret = agesa_locate_stage_file(fname, &rdev); else ret = agesa_locate_raw_file(fname, &rdev); @@ -119,7 +119,7 @@ const void *agesawrapper_locate_module(const char name[8]) file_size = region_device_sz(&rdev); /* Assume boot device is memory mapped so the mapping can leak. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); agesa = rdev_mmap_full(&rdev); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 8bc0f3663b..723b279aa3 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -290,7 +290,7 @@ static int psp_load_blob(int type, void *addr) { int cmd_status; - if (!IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); return PSPSTS_UNSUPPORTED; } diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 018975f098..1027ae0294 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -59,7 +59,7 @@ AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* XHCI configuration */ - if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)) + if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) FchParams_env->Usb.Xhci0Enable = TRUE; else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 3d7d833a96..227fb70136 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -91,7 +91,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; @@ -268,10 +268,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 0b297fa1f5..d4aabdb7af 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -16,7 +16,7 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) -If (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { +If (CONFIG(HAVE_ACPI_RESUME)) { Store(0x0D, SSFG) } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 37e22ac73d..9239030d6c 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -108,7 +108,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) + if (CONFIG(STONEYRIDGE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index a29c56c9da..1bd8cbf2f8 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -159,7 +159,7 @@ static void earliest_ramstage(void *unused) romstage_handoff_is_resume(); if (!s3_resume) { post_code(0x46); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); post_code(0x47); diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 45e659504b..6572e1a201 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -29,7 +29,7 @@ static void per_core_finalize(void *unused) if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (IS_ENABLED(CONFIG_SMM_TSEG)) { + if (CONFIG(SMM_TSEG)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 3212ec7cf7..15a41edce6 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -20,7 +20,7 @@ #include <arch/acpi.h> -#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE) +#if CONFIG(STONEYRIDGE_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index b1010142ef..613dd044f6 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -27,7 +27,7 @@ #define I2C_DEVICE_SIZE 0x00001000 #define I2C_DEVICE_COUNT 4 -#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE) +#if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 #endif #define HPET_BASE_ADDRESS 0xfed00000 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 68b5b08f1f..e3475eebcb 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -98,7 +98,7 @@ static void lpc_init(struct device *dev) /* Set up SERIRQ, enable continuous mode */ byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) byte |= PM_SERIRQ_MODE; pm_write8(PM_SERIRQ_CONF, byte); diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index eddaba4951..8a875d9206 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -199,7 +199,7 @@ void check_mca(void) i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (IS_ENABLED(CONFIG_ACPI_BERT) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 6c2637f26b..927cce0c1f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -237,7 +237,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, current += hest->header.length; /* BERT */ - if (IS_ENABLED(CONFIG_ACPI_BERT) && bert_errors_present()) { + if (CONFIG(ACPI_BERT) && bert_errors_present()) { /* Skip the table if no errors are present. ACPI driver reports * a table with a 0-length region: * BERT: [Firmware Bug]: table invalid. diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index d805683f71..edd5c2394e 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -36,7 +36,7 @@ uintptr_t restore_top_of_low_cacheable(void) return biosram_read32(BIOSRAM_CBMEM_TOP); } -#if IS_ENABLED(CONFIG_ACPI_BERT) +#if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 #else @@ -49,7 +49,7 @@ uintptr_t restore_top_of_low_cacheable(void) void bert_reserved_region(void **start, size_t *size) { - if (IS_ENABLED(CONFIG_ACPI_BERT)) + if (CONFIG(ACPI_BERT)) *start = cbmem_top(); else start = NULL; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 42f6f8a758..f2263b7aa9 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -93,7 +93,7 @@ asmlinkage void car_stage_entry(void) console_init(); - if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); mainboard_romstage_entry(s3_resume); @@ -132,7 +132,7 @@ asmlinkage void car_stage_entry(void) msr_t sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; wrmsr(SYSCFG_MSR, sys_cfg); - if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)) + if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); @@ -192,7 +192,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) if (!dev || !dev->chip_info) { printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ? + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; return; } diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 657ff493dc..c053d909f7 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -103,7 +103,7 @@ static void sb_apmc_smi_handler(void) acpi_write32(MMIO_ACPI_PM1_CNT_BLK, reg32); break; case APM_CNT_ELOG_GSMI: - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; } @@ -156,7 +156,7 @@ static void sb_slp_typ_handler(void) if (slp_typ >= ACPI_S3) { /* Sleep Type Elog S3, S4, and S5 entry */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); wbinvd(); @@ -183,7 +183,7 @@ static void sb_slp_typ_handler(void) * it and continue normal path. S3 will fail and the wake event * becomes a SCI. */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) { + if (CONFIG(ELOG_GSMI)) { reg16 = acpi_read16(MMIO_ACPI_PM1_EN); reg16 &= acpi_read16(MMIO_ACPI_PM1_STS); if (reg16) @@ -197,7 +197,7 @@ static void sb_slp_typ_handler(void) elog_add_extended_event( ELOG_SLEEP_PENDING_GPE0_WAKE, reg32); - } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */ + } /* if (CONFIG(ELOG_GSMI)) */ /* * An IO cycle is required to trigger the STPCLK/STPGNT diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 069fc7879c..2f32c5c86e 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -76,7 +76,7 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -553,7 +553,7 @@ static void sb_lpc_early_setup(void) dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); - if (IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)) { + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) { /* Decode SIOs at 2E/2F and 4E/4F */ dword = pci_read_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); @@ -742,7 +742,7 @@ static void sb_init_acpi_ports(void) /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ pm_write16(PM_ACPI_SMI_CMD, APM_CNT); configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); @@ -804,7 +804,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) static void sb_log_pm1_status(uint16_t pm1_sts) { - if (!IS_ENABLED(CONFIG_ELOG)) + if (!CONFIG(ELOG)) return; if (pm1_sts & WAK_STS) @@ -952,7 +952,7 @@ void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; - if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) + if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 409b9b1904..e6b1a36d16 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -29,7 +29,7 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> -#define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) static uintptr_t spibar; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 2358d71c57..98166b056f 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -370,7 +370,7 @@ static void soc_init(struct device *dev) /* Init ECAM, MDIO, PEM, PHY, QLM ... */ bdk_boot(); - if (IS_ENABLED(CONFIG_PAYLOAD_FIT_SUPPORT)) { + if (CONFIG(PAYLOAD_FIT_SUPPORT)) { struct device_tree_fixup *dt_fixup; dt_fixup = malloc(sizeof(*dt_fixup)); @@ -381,7 +381,7 @@ static void soc_init(struct device *dev) } } - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) soc_init_atf(); } diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index a512dffa00..c3f0866859 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -38,17 +38,17 @@ void bootblock_main(const uint64_t reg_x0, init_timer(); - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)) + if (CONFIG(COLLECT_TIMESTAMPS)) base_timestamp = timestamp_get(); /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) + if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) timestamp_init(base_timestamp); bootblock_soc_early_init(); bootblock_mainboard_early_init(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index c87b51cfbe..07cb2adef7 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -92,10 +92,10 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; @@ -128,7 +128,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); } - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 2475db39a1..d1402d9651 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -30,7 +30,7 @@ Method(_PRT) Package(){0x000FFFFF, 0, 0, CSE_INT}, Package(){0x0011FFFF, 0, 0, ISH_INT}, Package(){0x0012FFFF, 0, 0, SATA_INT}, -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) Package(){0x000CFFFF, 0, 0, CNVI_INT}, Package(){0x0013FFFF, 0, 0, PIRQF_INT}, Package(){0x0013FFFF, 1, 0, PIRQF_INT}, diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 799778bc3c..7c9c873ddb 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -45,6 +45,6 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* SGX */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 9f7304bb57..a7317fe82b 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -34,7 +34,7 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl" diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bb5eff8c8b..ac6903a9d2 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -38,7 +38,7 @@ #include <timestamp.h> static const struct pad_config tpm_spi_configs[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ #else PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ @@ -95,10 +95,10 @@ void bootblock_soc_early_init(void) pmc_global_reset_enable(0); /* Prepare UART for serial console. */ - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); - if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) + if (CONFIG(TPM_ON_FAST_SPI)) tpm_enable(); enable_pm_timer_emulation(); @@ -116,7 +116,7 @@ void bootblock_soc_early_init(void) /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ - if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) { + if (CONFIG(PAGING_IN_CACHE_AS_RAM)) { paging_set_nxe(1); paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6b8479d352..30a537b675 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -124,7 +124,7 @@ const char *soc_acpi_name(const struct device *dev) case 6: return "HS07"; case 7: return "HS08"; case 8: - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) return "HS09"; } break; @@ -300,7 +300,7 @@ static void set_power_limits(void) uint32_t tdp, min_power, max_power; uint32_t pl2_val; - if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); return; } @@ -527,7 +527,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GLK) case SA_DEVFN_IPU: silconfig->IpuEn = 0; break; @@ -558,7 +558,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these +#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; @@ -597,7 +597,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config static void glk_fsp_silicon_init_params_cb( struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { @@ -730,7 +730,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Disable monitor mwait since it is broken due to a hardware bug * without a fix. Specific to Apollolake. */ - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GLK)) silconfig->MonitorMwaitEnable = 0; silconfig->SkipMpInit = !chip_get_fsp_mp_init(); @@ -746,7 +746,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; /* Bios config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); @@ -847,7 +847,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) * Override GLK xhci clock gating register(XHCLKGTEN) to * mitigate usb device suspend and resume failure. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) { + if (CONFIG(SOC_INTEL_GLK)) { uint32_t *cfg; const struct resource *res; uint32_t reg; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index a08f1f0352..741e08c9b7 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -46,7 +46,7 @@ #include <soc/pm.h> static const struct reg_script core_msr_script[] = { -#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GLK) /* Enable C-state and IO/MWAIT redirect */ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK @@ -73,7 +73,7 @@ void soc_core_init(struct device *cpu) /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) || + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) mca_configure(NULL); @@ -87,20 +87,20 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ - if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); cpu_disable_eist(); - } else if (IS_ENABLED(CONFIG_APL_SET_MIN_CLOCK_RATIO)) { + } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); cpu_disable_eist(); } } -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) static void soc_init_core(struct device *cpu) { soc_core_init(cpu); @@ -139,7 +139,7 @@ static struct smm_relocation_attrs relo_attrs; /* * Do essential initialization tasks before APs can be fired up. * - * IF (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - + * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, * that are set prior to ramstage. * Real MTRRs are programmed after resource allocation. @@ -155,7 +155,7 @@ static struct smm_relocation_attrs relo_attrs; */ static void pre_mp_init(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { fsps_load(romstage_handoff_is_resume()); return; } @@ -163,7 +163,7 @@ static void pre_mp_init(void) x86_mtrr_check(); } -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) +#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) { msr_t msr; @@ -247,7 +247,7 @@ static void post_mp_init(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) mp_run_on_all_cpus(sgx_configure, NULL, 2000); } @@ -270,13 +270,13 @@ void soc_init_cpus(struct bus *cpu_bus) void apollolake_init_cpus(struct device *dev) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) return; soc_init_cpus(dev->link_list); /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 85a2b197df..82226ecf43 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -222,7 +222,7 @@ static void dump_cse_version(void *unused) * Print ME version only if UART debugging is enabled. Else, it takes * ~0.6 second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 9be598f61a..a05d6087be 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -35,14 +35,14 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *const dev) { - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) return; uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 20d2993ce2..939c449159 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -17,7 +17,7 @@ #ifndef _SOC_APL_GPIO_H_ #define _SOC_APL_GPIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #include <soc/gpio_glk.h> #else #include <soc/gpio_apl.h> diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 264704c755..d591c21b58 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -20,7 +20,7 @@ /* * Port ids. */ -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #define PID_GPIO_AUDIO 0xC9 #define PID_GPIO_SCC 0xC8 #else diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 61c97cebb5..d3538342b0 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -71,7 +71,7 @@ #define SMI_EOS 1 #define SMI_GBL 0 -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) #define ESPI_SMI_EN (1 << SMI_ESPI) /* Valid for GLK with ESPI */ #else #define ESPI_SMI_EN 0 @@ -190,7 +190,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 + 4*(x)) -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) #define PMC_GPE_AUDIO_31_0 9 #define PMC_GPE_N_95_64 8 #define PMC_GPE_N_63_32 7 diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82ae0a..ceed8f268f 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -43,8 +43,8 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) } static const struct pad_config lpc_gpios[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) -#if !IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT0 */ @@ -69,7 +69,7 @@ static const struct pad_config lpc_gpios[] = { * will keep LPC Controller awake and prevent S0ix entry */ PAD_NC(GPIO_154, NONE), -#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */ +#endif /* !CONFIG(SOC_ESPI) */ #else PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 889bbde66d..038fa9fb2b 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -166,7 +166,7 @@ static const struct fsp_speed_profiles glk_profile = { static const struct fsp_speed_profiles *get_fsp_profile(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) return &glk_profile; else return &apl_profile; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index a69a5cb116..ba1433c53b 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -30,7 +30,7 @@ void *cbmem_top(void) const config_t *config; void *tolum = (void *)sa_get_tseg_base(); - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GLK)) return tolum; dev = dev_find_slot(0, PCH_DEVFN_LPC); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ad4b5b0b2f..bef7052cea 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void soc_early_romstage_init(void) pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); } @@ -159,7 +159,7 @@ static bool punit_init(void) PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK; - if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) { + if (!CONFIG(SOC_INTEL_GLK)) { data = MCHBAR32(0x7818); data &= 0xFFFFE01F; data |= 0x20 | 0x200; @@ -277,8 +277,8 @@ asmlinkage void car_stage_entry(void) static void fill_console_params(FSPM_UPD *mupd) { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) { + if (CONFIG(CONSOLE_SERIAL)) { + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) { mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ @@ -287,7 +287,7 @@ static void fill_console_params(FSPM_UPD *mupd) mupd->FspmConfig.SerialDebugPortStrideSize = 2; /* used only for port type set to external */ mupd->FspmConfig.SerialDebugPortAddress = 0; - } else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { + } else if (CONFIG(DRIVERS_UART_8250IO)) { /* use external UART for debug */ mupd->FspmConfig.SerialDebugPortDevice = 3; /* use I/O port type */ @@ -320,7 +320,7 @@ static void check_full_retrain(const FSPM_UPD *mupd) static void soc_memory_init_params(FSPM_UPD *mupd) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); @@ -351,7 +351,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) static void parse_devicetree_setting(FSPM_UPD *m_upd) { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); if (!dev) return; @@ -368,7 +368,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) fill_console_params(mupd); - if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); mainboard_memory_init_params(mupd); @@ -385,7 +385,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * as designed. */ mupd->FspmConfig.SkipCseRbp = - IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + CONFIG(BOOT_DEVICE_MEMORY_MAPPED); /* * Converged Security Engine (CSE) has secure storage functionality. @@ -407,7 +407,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { /* Assume leaking is ok. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index cbb0c8c29a..7a3400ed3b 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -50,7 +50,7 @@ const smi_handler_t southbridge_smi[32] = { [GPIO_SMI_STS] = smihandler_southbridge_gpi, [TCO_SMI_STS] = smihandler_southbridge_tco, [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif }; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 875bc49575..66a1a1abcc 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -28,7 +28,7 @@ /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GLK) { .console_index = 0, .gpios = { diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 666a9daaf3..c322cce0ad 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -83,15 +83,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index bc8e877697..09d13221b3 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,7 +281,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 827c706cca..d20859d055 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -25,7 +25,7 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); void set_max_freq(void); void southcluster_enable_dev(struct device *dev); -#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) +#if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index b65c6809a9..3e8b6a27ef 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -39,7 +39,7 @@ void punit_init(void); void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) +#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); #else static inline void byt_config_com1_and_enable(void) { } diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 0869c7b656..5f33c86c9b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -131,7 +131,7 @@ static void nc_read_resources(struct device *dev) reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 550f8724c3..dfc5366733 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -112,7 +112,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; - mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); + mp->rmt_enabled = CONFIG(MRC_RMT); /* Default to 2GiB IO hole. */ if (!mp->io_hole_mb) @@ -124,7 +124,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->saved_data_size = region_device_sz(&rdev); mp->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (prev_sleep_state == ACPI_S3) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -157,7 +157,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + #if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7ea1443ed6..5621dd16eb 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <elog.h> @@ -193,7 +193,7 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -224,7 +224,7 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (prev_sleep_state != ACPI_S3) boot_count_increment(); #endif diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index c722f5c1f2..1bc9ed1c34 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -113,7 +113,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -209,7 +209,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -242,7 +242,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -347,7 +347,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -373,7 +373,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 9dd89d2a8d..1faf6516b3 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -134,7 +134,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 4ace22aab9..dbd29503c7 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -89,15 +89,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -492,12 +492,12 @@ unsigned long southcluster_write_acpi_tables(struct device *device, acpi_header_t *ssdt2; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!IS_ENABLED(CONFIG_DISABLE_HPET)) { + if (!CONFIG(DISABLE_HPET)) { current = acpi_write_hpet(device, current, rsdp); current = acpi_align_current(current); } - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) { + if (CONFIG(INTEL_GMA_ADD_VBT)) { igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); @@ -543,7 +543,7 @@ void southcluster_inject_dsdt(struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); /* Fill in the Wifi Region id */ - if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) + if (CONFIG(HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 067b05f6de..6b2ececc40 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -48,7 +48,7 @@ Device (LPCB) }) } -#if !IS_ENABLED(CONFIG_DISABLE_HPET) +#if !CONFIG(DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 023a5b9ee0..16751fbadd 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -67,7 +67,7 @@ static void gfx_init(struct device *dev) printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) { + if (!CONFIG(RUN_FSP_GOP)) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5d8c332feb..5063342955 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,7 +242,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d2653f3093..207c843d52 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -37,7 +37,7 @@ void smm_region(void **start, size_t *size) size_t mmap_region_granularity(void) { /* Align to TSEG size when SMM is in use, and 8MiB by default */ - return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size() + return CONFIG(HAVE_SMI_HANDLER) ? smm_region_size() : 8 << 20; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index c54c2c8f3c..9267448697 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -165,7 +165,7 @@ static void nc_read_resources(struct device *dev) size_k = RES_IN_KIB(0x00100000); mmio_resource(dev, index++, base_k, size_k); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); } diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 5fe3550509..e4180641a6 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params, config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 1f02269cec..a72330915e 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -153,7 +153,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -259,7 +259,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -292,7 +292,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -345,7 +345,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -368,7 +368,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index fa22cf7c06..c87232dd92 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -119,7 +119,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(void *addr) { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index aa2dd2ad8e..e51c9bf7ce 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -169,15 +169,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index aab8045f3f..6383e15e79 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -30,7 +30,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, #endif }; diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 964534831d..1adbbc8aa2 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -56,7 +56,7 @@ const struct reg_script system_agent_finalize_script[] = { }; const struct reg_script pch_finalize_script[] = { -#if !IS_ENABLED(CONFIG_SPI_CONSOLE) +#if !CONFIG(SPI_CONSOLE) /* Set SPI opcode menu */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP, SPI_OPPREFIX), diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 94ec3a72f8..319549df1e 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -512,7 +512,7 @@ static void igd_init(struct device *dev) /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) if (display_init_required() || vboot_wants_oprom()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 7292bcf386..71c7999e5b 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -23,7 +23,7 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); void broadwell_pch_enable_dev(struct device *dev); -#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) +#if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); #else static inline void broadwell_run_reference_code(void) { } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 63db9aaafc..c831c2c5bc 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -219,7 +219,7 @@ static const struct reg_script pch_misc_init_script[] = { REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END @@ -429,7 +429,7 @@ static void pch_cg_init(struct device *dev) static void pch_set_acpi_mode(void) { -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); @@ -621,7 +621,7 @@ static unsigned long broadwell_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) + if (CONFIG(INTEL_PCH_UART_CONSOLE)) current = acpi_write_dbg2_pci_uart(rsdp, current, (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? PCH_DEV_UART1 : PCH_DEV_UART0, diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 73317e3e71..dd5e5b870c 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -40,7 +40,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -58,7 +58,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -483,7 +483,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -703,7 +703,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -792,7 +792,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -804,7 +804,7 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data) { me_print_fw_version(mbp_data->fw_version_name); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) me_print_fwcaps(mbp_data->fw_capabilities); #endif @@ -912,7 +912,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) } /* Dump out the MBP contents. */ -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); for (i = 0; i < mbp->header.mbp_size - 1; i++) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 3fd5ea4f10..32135eedbb 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -555,7 +555,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - if (IS_ENABLED(CONFIG_PCIEXP_AER)) + if (CONFIG(PCIEXP_AER)) pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); else @@ -563,7 +563,7 @@ static void pch_pcie_early(struct device *dev) (1 << 29)); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + if (CONFIG(PCIEXP_L1_SUB_STATE)) pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); else pci_update_config32(dev, 0x200, ~0xfffff, 0); diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 291d5eb9ea..ca22b4ef5b 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -57,7 +57,7 @@ static int prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index acb435bce0..04657aebd8 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -24,7 +24,7 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #endif @@ -57,7 +57,7 @@ void raminit(struct pei_data *pei_data) pei_data->saved_data_size = region_device_sz(&rdev); pei_data->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data) if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9aa31b85c1..2531665f1f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -123,7 +123,7 @@ void romstage_common(struct romstage_params *params) params->pei_data->boot_mode = params->power_state->prev_sleep_state; -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 0330acb91b..59fb4f7a7e 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -41,7 +41,7 @@ static void serialio_enable_d3hot(struct resource *res) static int serialio_uart_is_debug(struct device *dev) { -#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) +#if CONFIG(INTEL_PCH_UART_CONSOLE) switch (dev->path.pci.devfn) { case PCH_DEVFN_UART0: /* UART0 */ return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); @@ -278,7 +278,7 @@ static void serialio_set_resources(struct device *dev) { pci_dev_set_resources(dev); -#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) +#if CONFIG(INTEL_PCH_UART_CONSOLE) /* Update UART base address if used for debug */ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 9f5d81dc31..b36b99dd4e 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -178,7 +178,7 @@ static void southbridge_smi_sleep(void) /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -292,7 +292,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -325,7 +325,7 @@ static void finalize(void) } finalize_done = 1; -#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) +#if CONFIG(SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -371,7 +371,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -390,7 +390,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 21417cf828..d8127577db 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -133,7 +133,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 3912688181..aef1d1cd44 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -384,7 +384,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); *resource_cnt = index; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 127d9c8b64..639f6c6f90 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -204,14 +204,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; } else diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 1806e75e87..cdfff911b8 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -112,7 +112,7 @@ Scope (\_SB.PCI0) { And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ GPMO(SD_PWR_EN_PIN, 0x1) #endif @@ -126,7 +126,7 @@ Scope (\_SB.PCI0) { Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */ GPMO(SD_PWR_EN_PIN, 0x0) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ae8de6a1df..d9ff70b6bc 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -30,7 +30,7 @@ #include "scs.asl" /* GPIO controller */ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include "gpio_cnp_h.asl" #else #include "gpio.asl" diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 08a13ea860..5555969289 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <soc/pch.h> -#if IS_ENABLED(CONFIG_FSP_CAR) +#if CONFIG(FSP_CAR) #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { @@ -53,7 +53,7 @@ void bootblock_soc_early_init(void) bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 3ebe1e48e6..f60f319999 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -21,7 +21,7 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 018ccfc467..1c7fd7f082 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -162,7 +162,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a643954a91..993e7f3d4a 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -29,7 +29,7 @@ #include <soc/ramstage.h> #include <string.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -195,7 +195,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ab7c765043..3e4bafc322 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -30,7 +30,7 @@ #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #else #include <soc/gpio_defs.h> @@ -107,7 +107,7 @@ struct soc_intel_cannonlake_config { enum { SaGv_Disabled, SaGv_FixedLow, -#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index e97b5711e8..db001b82ae 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -90,7 +90,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, die("spd.bin not found or incorrect index\n"); spd_data_len = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 19ff171eb8..6bedb81390 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -497,7 +497,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) return 0; /* diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1ebde35e05..318b8a25ae 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -213,7 +213,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } else { params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = - IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); + CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } dev = dev_find_slot(0, PCH_DEVFN_UFS); diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 2b3c9007a4..015220d249 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (CONFIG(INTEL_GMA_ADD_VBT)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 718372ddc1..e7056ebcec 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -16,7 +16,7 @@ #ifndef _SOC_CANNONLAKE_GPIO_H_ #define _SOC_CANNONLAKE_GPIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include <soc/gpio_defs_cnp_h.h> #define CROS_GPIO_DEVICE_NAME "INT3450:00" #else diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index c3957d39c8..95cca65ab2 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -116,7 +116,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index 9121ac3031..e38c3381d8 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,7 +50,7 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 5dffb8197e..7c6025cb75 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -227,7 +227,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 8ffda2a57b..b2dd26dcf0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -147,7 +147,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8b2c1798c..5597c4f230 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -34,7 +34,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; - if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)) + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) m_cfg->UserBd = BOARD_TYPE_DESKTOP; else m_cfg->UserBd = BOARD_TYPE_ULT_ULX; @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 5f9e0f82af..643fad645f 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -93,7 +93,7 @@ void smihandler_soc_at_finalize(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index d3860dd76c..6c52bbfd77 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -13,11 +13,11 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_ACPI_CONSOLE) +#if CONFIG(ACPI_CONSOLE) #include <soc/iomap.h> -Name (UFLG, IS_ENABLED(CONFIG_CONSOLE_SERIAL)) +Name (UFLG, CONFIG(CONSOLE_SERIAL)) Method (LURT, 1, Serialized) { @@ -57,7 +57,7 @@ Method (APRT, 1, Serialized) } Store (INDX, LENG) /* Length of the String */ -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) +#if CONFIG(DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) Field (UBAR, AnyAcc, NoLock, Preserve) diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 01913b51c5..bdc0d5c15c 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -34,7 +34,7 @@ Method (_PTS, 1) { Store (POST_OS_ENTER_PTS, DBG0) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) +#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) /* Call EC _PTS handler */ \_SB.PCI0.LPCB.EC0.PTS (Arg0) #endif @@ -46,7 +46,7 @@ Method (_WAK, 1) { Store (POST_OS_ENTER_WAKE, DBG0) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) +#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) /* Call EC _WAK handler */ \_SB.PCI0.LPCB.EC0.WAK (Arg0) #endif diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0027744003..e311ae6210 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -180,7 +180,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, return generic_pm1_en; } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) +#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* * Save wake source information for calculating ACPI _SWS values * @@ -452,7 +452,7 @@ void generate_cpu_entries(struct device *device) acpigen_write_processor_cnot(cores_per_package); } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) +#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 17b8dc063c..d3ee671bef 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -167,11 +167,11 @@ clear_var_mtrr: invd mov %eax, %cr0 -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) jmp car_nem -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) jmp car_cqos -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) jmp car_nem_enhanced #else jmp .halt_forever /* In case nothing has selected */ @@ -221,7 +221,7 @@ fixed_mtrr_list: .word MTRR_FIX_4K_F8000 fixed_mtrr_list_size = . - fixed_mtrr_list -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) .global car_nem car_nem: /* Disable cache eviction (setup stage) */ @@ -252,7 +252,7 @@ car_nem: jmp car_init_done -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) .global car_cqos car_cqos: /* @@ -356,7 +356,7 @@ car_cqos: jmp car_init_done -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: /* Disable cache eviction (setup stage) */ diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index a4d16e8022..ab7886cb36 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -23,7 +23,7 @@ .global chipset_teardown_car chipset_teardown_car: -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) /* * Since Page table is located in CAR, disable paging before CAR * teardown. Also clear CR3 and CR4.PAE. @@ -50,7 +50,7 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr -#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +#if CONFIG(INTEL_CAR_NEM) .global car_nem_teardown car_nem_teardown: @@ -65,7 +65,7 @@ car_nem_teardown: and $(~(1 << 0)), %eax wrmsr -#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +#elif CONFIG(INTEL_CAR_CQOS) .global car_cqos_teardown car_cqos_teardown: @@ -86,7 +86,7 @@ car_cqos_teardown: and $~IA32_PQR_ASSOC_MASK, %edx wrmsr -#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +#elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced_teardown car_nem_enhanced_teardown: diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index d196f6195f..2e3b99e167 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -157,7 +157,7 @@ void fast_spi_lock_bar(void) void *spibar = fast_spi_get_bar(); uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN; - if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS)) + if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS)) hsfs |= SPIBAR_HSFSTS_WRSDIS; write16(spibar + SPIBAR_HSFSTS_CTL, hsfs); diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d77e052c96..0065a6c54f 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -35,7 +35,7 @@ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \ PAD_CFG1_PULL_MASK | \ PAD_CFG1_TOL_MASK | \ @@ -190,7 +190,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, if (ENV_SMM) return; - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) return; int irq; @@ -276,7 +276,7 @@ static void gpio_configure_pad(const struct pad_config *cfg) /* Patch GPIO settings for SoC specifically */ soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf); - if (IS_ENABLED(CONFIG_DEBUG_GPIO)) + if (CONFIG(DEBUG_GPIO)) printk(BIOS_DEBUG, "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" " : 0x%08x]\n", @@ -411,7 +411,7 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num) const struct pad_community *comm; size_t group, pin; - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES)) return relative_pad_in_comm(gpio_get_community(gpio_num), gpio_num); @@ -489,7 +489,7 @@ void gpi_clear_get_smi_status(struct gpi_status *sts) comm++; } - if (IS_ENABLED(CONFIG_DEBUG_SMI)) + if (CONFIG(DEBUG_SMI)) print_gpi_status(sts); } @@ -560,7 +560,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) MISCCFG_GPE0_DW1_MASK | MISCCFG_GPE0_DW0_MASK); - if (IS_ENABLED(CONFIG_DEBUG_GPIO)) + if (CONFIG(DEBUG_GPIO)) printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", misccfg_mask, misccfg_value); comm = soc_gpio_get_community(&gpio_communities); diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 3e58d60e2e..81eb7eedec 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -355,7 +355,7 @@ static uint32_t gspi_csctrl_state_v1(uint32_t pol, enum cs_assert cs_assert) static uint32_t gspi_csctrl_state(uint32_t pol, enum cs_assert cs_assert) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) return gspi_csctrl_state_v2(pol, cs_assert); return gspi_csctrl_state_v1(pol, cs_assert); @@ -379,7 +379,7 @@ static uint32_t gspi_csctrl_polarity_v1(enum spi_polarity active_pol) static uint32_t gspi_csctrl_polarity(enum spi_polarity active_pol) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2)) return gspi_csctrl_polarity_v2(active_pol); return gspi_csctrl_polarity_v1(active_pol); diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 376a40d3cf..8ab835e577 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -23,7 +23,7 @@ #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) static void codecs_init(uint8_t *base, u32 codec_mask) { int i; @@ -65,7 +65,7 @@ static struct device_operations hda_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9021..0ad3e5c32a 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -76,7 +76,7 @@ #define PAD_CFG1_PULL_UP_20K (0xc << 10) #define PAD_CFG1_PULL_UP_667 (0xd << 10) #define PAD_CFG1_PULL_NATIVE (0xf << 10) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) /* Tx enabled driving last value driven, Rx enabled */ #define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14) /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller @@ -125,7 +125,7 @@ #define PAD_CFG2_DEBOUNCE_MASK 0x1f /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_CFG1_TOL_MASK (0x1 << 25) #define PAD_CFG1_TOL_1V8 (0x1 << 25) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */ @@ -134,7 +134,7 @@ #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value #else @@ -147,7 +147,7 @@ PAD_CFG0_TRIG_##trig | \ PAD_CFG0_RX_POL_##inv) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ @@ -180,7 +180,7 @@ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(TxLASTRxE)) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS */ @@ -269,7 +269,7 @@ */ #define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ @@ -384,7 +384,7 @@ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 494a1b0fed..b383637736 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -240,7 +240,7 @@ void lpc_io_setup_comm_a_b(void) uint16_t com_enable = LPC_IOE_COMA_EN; /* ComB Range 2F8h-2FFh [6:4] */ - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { com_ranges |= LPC_IOD_COMB_RANGE; com_enable |= LPC_IOE_COMB_EN; } diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c191ad06cd..0a5e1bf4d6 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -46,7 +46,7 @@ static void pch_pcie_init(struct device *dev) /* disable parity error response, enable ISA */ pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2); - if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) { + if (CONFIG(PCIE_DEBUG_INFO)) { printk(BIOS_SPEW, " MBL = 0x%08x\n", pci_read_config32(dev, PCI_MEMORY_BASE)); printk(BIOS_SPEW, " PMBL = 0x%08x\n", diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 61991c2f55..4a35a03ff1 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -25,7 +25,7 @@ #error "PCR_BASE_ADDRESS need to be non-zero!" #endif -#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) +#if !CONFIG(PCR_COMMON_IOSF_1_0) #define PCR_SBI_CMD_TIMEOUT 10 /* 10ms */ @@ -76,7 +76,7 @@ static void *__pcr_reg_address(uint8_t pid, uint16_t offset) void *pcr_reg_address(uint8_t pid, uint16_t offset) { - if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)) + if (CONFIG(PCR_COMMON_IOSF_1_0)) assert(IS_ALIGNED(offset, sizeof(uint32_t))); return __pcr_reg_address(pid, offset); @@ -91,7 +91,7 @@ void *pcr_reg_address(uint8_t pid, uint16_t offset) */ static inline void check_pcr_offset_align(uint16_t offset, size_t size) { - const size_t align = IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) ? + const size_t align = CONFIG(PCR_COMMON_IOSF_1_0) ? sizeof(uint32_t) : size; assert(IS_ALIGNED(offset, align)); @@ -219,7 +219,7 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata) pcr_write8(pid, offset, data8); } -#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) +#if !CONFIG(PCR_COMMON_IOSF_1_0) #ifdef __SIMPLE_DEVICE__ static int pcr_wait_for_completion(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1f25d756f3..43543a1cc5 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -66,7 +66,7 @@ static void pch_pmc_add_io_resources(struct device *dev, cfg->abase_addr, cfg->abase_size, IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); - if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) { + if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) { /* * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've * observed cases where the BAR reads back as 0, but the IO @@ -105,7 +105,7 @@ static void pch_pmc_read_resources(struct device *dev) void pmc_set_acpi_mode(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 6c967adfb0..f58d36246e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -384,7 +384,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -432,7 +432,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps) return ps->prev_sleep_state; } -#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK) +#if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index 2d70de273b..5a0d45cc0f 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -53,7 +53,7 @@ void rtc_conf_set_bios_interface_lockdown(void) PCR_RTC_CONF_BILD); } -#if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP) +#if CONFIG(INTEL_HAS_TOP_SWAP) void configure_rtc_buc_top_swap(enum ts_config ts_state) { pcr_rmw32(PID_RTC, PCR_RTC_BUC, ~PCR_RTC_BUC_TOP_SWAP, ts_state); diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 4c32520123..0801cb77c4 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -52,7 +52,7 @@ static void sata_final(struct device *dev) /* Read Ports Implemented (GHC_PI) */ port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); - if (IS_ENABLED(CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT)) + if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; port_impl &= 0x07; /* bit 0-2 */ diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index ea8d1b02bc..2794a3b82e 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -19,7 +19,7 @@ #include <device/pci_ids.h> #include <intelblocks/sd.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void sd_fill_ssdt(struct device *dev) { const char *path; @@ -59,7 +59,7 @@ static struct device_operations dev_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = sd_fill_ssdt, #endif .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index f1a2ca0874..1a215eb69d 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -133,7 +133,7 @@ static void tco_enable_bar(void) */ void tco_configure(void) { - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)) tco_enable_bar(); tco_timer_disable(); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0c10d6be49..16bb3a2d1d 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -192,7 +192,7 @@ void smihandler_southbridge_sleep( mainboard_smi_sleep(slp_typ); /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3 && IS_ENABLED(CONFIG_ELOG_GSMI)) + if (slp_typ >= ACPI_S3 && CONFIG(ELOG_GSMI)) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ @@ -324,7 +324,7 @@ static void finalize(void) } finalize_done = 1; - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); @@ -361,13 +361,13 @@ void smihandler_southbridge_apmc( break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) pmc_enable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmc_enable_pm1_control(SCI_EN); - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) pmc_disable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; @@ -387,11 +387,11 @@ void smihandler_southbridge_apmc( } break; case APM_CNT_ELOG_GSMI: - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); break; case APM_CNT_SMMSTORE: - if (IS_ENABLED(CONFIG_SMMSTORE)) + if (CONFIG(SMMSTORE)) southbridge_smi_store(save_state_ops); break; case APM_CNT_FINALIZE: @@ -414,7 +414,7 @@ void smihandler_southbridge_pm1( */ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ - if (IS_ENABLED(CONFIG_ELOG_GSMI)) + if (CONFIG(ELOG_GSMI)) elog_add_event(ELOG_TYPE_POWER_BUTTON); pmc_disable_pm1_control(-1UL); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d929975186..dd8bab3483 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -95,7 +95,7 @@ void smm_region_info(void **start, size_t *size) *size = sa_get_tseg_size(); } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) static void smm_disable_espi(void *dest) { pmc_disable_smi(ESPI_SMI_EN); diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index c02cfed6a9..85db5cfa4a 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -26,7 +26,7 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) +#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI) { .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, #endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index f9782aaa38..d95a4ebedb 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -160,7 +160,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) uintptr_t top_of_ram; int index = *resource_count; - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) dpr_size = sa_get_dpr_size(); /* Get SoC reserve memory size as per user selection */ @@ -270,7 +270,7 @@ static void systemagent_read_resources(struct device *dev) soc_add_fixed_mmio_resources(dev, &index); /* Calculate and add DRAM resources. */ sa_add_dram_resources(dev, &index); - if (IS_ENABLED(CONFIG_SA_ENABLE_IMR)) + if (CONFIG(SA_ENABLE_IMR)) /* Add the isolated memory ranges (IMRs). */ sa_add_imr_resources(dev, &index); } @@ -292,7 +292,7 @@ static struct device_operations systemagent_ops = { .enable_resources = pci_dev_enable_resources, .init = soc_systemagent_init, .ops_pci = &pci_dev_ops_pci, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7f105d7e17..7f213722de 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -45,7 +45,7 @@ static void uart_lpss_init(uintptr_t baseaddr) CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +#if CONFIG(DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { /* return Base address for UART console index */ @@ -92,7 +92,7 @@ struct device *uart_get_device(void) * config option is not selected. * By default return NULL in this case to avoid compilation errors. */ - if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) return NULL; int console_index = uart_get_valid_index(); @@ -141,7 +141,7 @@ void uart_bootblock_init(void) uart_common_init(uart_get_device(), UART_BASE(CONFIG_UART_FOR_CONSOLE)); - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + if (!CONFIG(DRIVERS_UART_8250MEM_32)) /* Put UART in byte access mode for 16550 compatibility */ soc_uart_set_legacy_mode(); @@ -156,7 +156,7 @@ static void uart_read_resources(struct device *dev) pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) && + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ @@ -204,7 +204,7 @@ static bool uart_controller_needs_init(struct device *dev) * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing * controller here. */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) return false; /* If this device does not correspond to debug port, then skip. */ diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index f1bb93551e..c429e7dd58 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -29,7 +29,7 @@ static struct device_operations usb_xhci_ops = { .init = soc_xhci_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_usb_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif }; diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 8ccea5d6a1..6f79466b10 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -58,7 +58,7 @@ static void dmi_lockdown_cfg(void) static void fast_spi_lockdown_cfg(int chipset_lockdown) { - if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI)) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)) return; /* Set FAST_SPI opcode menu */ diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 0bc3039064..60fe0d861e 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -22,7 +22,7 @@ void *vbt_get(void) { - if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (!CONFIG(RUN_FSP_GOP)) return NULL; /* Normal mode and S3 resume path PEIM GFX init is not needed. diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 7633637950..f3e91ff451 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -83,7 +83,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = top_of_32bit_ram(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif @@ -140,7 +140,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = get_pmbase(); /* System Management */ - if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (!CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = 0x00; fadt->acpi_enable = 0x00; fadt->acpi_disable = 0x00; diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 110d67d6de..f16ee20620 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -58,13 +58,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { -#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) +#if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif }; void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); }; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 955bf4b936..baa0878f5e 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -41,7 +41,7 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func, reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base; pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16); -#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE)) +#if (CONFIG(NON_LEGACY_UART_MODE)) /* Decode MMIO at MEMBA (BAR1) */ pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1, CONFIG_CONSOLE_UART_BASE_ADDRESS + @@ -53,12 +53,12 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func, */ pci_write_config16(uart_dev, PCI_COMMAND, pci_read_config16(uart_dev, PCI_COMMAND) | -#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE)) +#if (CONFIG(NON_LEGACY_UART_MODE)) PCI_COMMAND_MEMORY | #endif PCI_COMMAND_MASTER | PCI_COMMAND_IO); -#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_230400)) +#if (CONFIG(CONSOLE_SERIAL_230400)) /* Change the highest speed to 230400 */ uint32_t *psr_reg = (uint32_t *)(CONFIG_CONSOLE_UART_BASE_ADDRESS + diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 29bea2b60f..68bd60c83a 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -50,7 +50,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = denverton_init_cpus, .scan_bus = NULL, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index c70c22ad98..e4aa78f291 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -44,7 +44,7 @@ void soc_save_dimm_info(void) return; /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ - if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (CONFIG(DISPLAY_HOBS)) soc_display_fsp_smbios_memory_info_hob(memory_info_hob); /* diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index f5df21a792..af840a2f1a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -264,7 +264,7 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index c937709255..25d7c9d390 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -210,7 +210,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -310,7 +310,7 @@ void southcluster_enable_dev(struct device *dev) static struct device_operations device_ops = { .read_resources = lpc_read_resources, .set_resources = pci_dev_set_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, #endif diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 7d623dabf4..514d86d5b5 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -51,7 +51,7 @@ u32 top_of_32bit_ram(void) /* * Add IQAT region size if enabled. */ -#if IS_ENABLED(CONFIG_IQAT_ENABLE) +#if CONFIG(IQAT_ENABLE) iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE; #endif return system_agent_region_base(TOLUD) - diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 193e41c2fc..8b520873e5 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -38,7 +38,7 @@ static void pch_power_options(struct device *dev) { /* TODO */ } static void pch_set_acpi_mode(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 77364b80d2..4477c927e9 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -34,7 +34,7 @@ void __weak mainboard_config_gpios(void) {} -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) static void display_fsp_smbios_memory_info_hob(void) { const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; @@ -141,7 +141,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -157,7 +157,7 @@ asmlinkage void car_stage_entry(void) fsp_memory_init(false); -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +#if CONFIG(DISPLAY_HOBS) display_fsp_smbios_memory_info_hob(); #endif @@ -176,7 +176,7 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -200,7 +200,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ - m_cfg->PcdEnableIQAT = IS_ENABLED(CONFIG_IQAT_ENABLE); + m_cfg->PcdEnableIQAT = CONFIG(IQAT_ENABLE); /* if ME HECI communication is disabled, apply default one*/ if (mupd->FspmConfig.PcdMeHeciCommunication == 0) { diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 9961778321..4d748b2a71 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -209,7 +209,7 @@ static void finalize(void) } finalize_done = 1; - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); } diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index ac779d050d..07e07045f5 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -34,7 +34,7 @@ static void dnv_ns_uart_read_resources(struct device *dev) { /* read resources to be visible in the log*/ pci_dev_read_resources(dev); - if (!IS_ENABLED(CONFIG_LEGACY_UART_MODE)) + if (!CONFIG(LEGACY_UART_MODE)) return; struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res == NULL) @@ -88,6 +88,6 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) { if (phase != END_OF_FIRMWARE) return; - if (IS_ENABLED(CONFIG_LEGACY_UART_MODE)) + if (CONFIG(LEGACY_UART_MODE)) hide_hsuarts(); } diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 9701a338eb..371581b77a 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -89,7 +89,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index ae958c2f01..8e47f5c7a0 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -16,7 +16,7 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) Name(\_S3, Package(){0x5,0x5,0x0,0x0}) #endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 89ea4c2ada..15dc851b96 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -150,7 +150,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void enable_smis(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 3786c0cc35..c9cbcfe960 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -307,7 +307,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 282083aa55..8d4e090a40 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -207,7 +207,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, } } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) southcluster_smm_save_gpio_route(route_reg); #endif } diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index b28b195c87..75daba540e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,7 +283,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index ce66df8a6a..9cbc95c240 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -39,7 +39,7 @@ void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); -#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) +#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); #else static inline void byt_config_com1_and_enable(void) { } diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 62cc189b60..b4eb006aab 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -63,7 +63,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) if (pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S4: @@ -229,7 +229,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index ee0929d83d..f2abd9975a 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -207,7 +207,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -274,7 +274,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -293,7 +293,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 8fce928a2d..e6947b4d6d 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -139,7 +139,7 @@ static void sc_enable_serial_irqs(struct device *dev) write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) /* * SoC requires that the System BIOS first set the SERIRQ logic to * continuous mode operation for at least one frame before switching diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4bc924c500..573c1c4390 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -138,7 +138,7 @@ enum { static uint8_t readb_(const void *addr) { uint8_t v = read8(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -148,7 +148,7 @@ static uint8_t readb_(const void *addr) static uint16_t readw_(const void *addr) { uint16_t v = read16(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -158,7 +158,7 @@ static uint16_t readw_(const void *addr) static uint32_t readl_(const void *addr) { uint32_t v = read32(addr); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", v, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -168,7 +168,7 @@ static uint32_t readl_(const void *addr) static void writeb_(uint8_t b, void *addr) { write8(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -177,7 +177,7 @@ static void writeb_(uint8_t b, void *addr) static void writew_(uint16_t b, void *addr) { write16(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } @@ -186,7 +186,7 @@ static void writew_(uint16_t b, void *addr) static void writel_(uint32_t b, void *addr) { write32(addr, b); - if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", b, (((uint32_t) addr) & SPI_OFFSET_MASK)); } diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index f6dd2a7021..348e1c00f1 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -30,7 +30,7 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *domain_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -45,7 +45,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = domain_acpi_name #endif }; diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index b8ef6b18b4..54e796d48d 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -51,22 +51,22 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Serial Port */ - if (IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (CONFIG(INTEGRATED_UART)) { UpdData->SerialPortConfigure = 1; /* values are from FSP .bsf file */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_9600)) + if (CONFIG(CONSOLE_SERIAL_9600)) UpdData->SerialPortBaudRate = 8; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_19200)) + else if (CONFIG(CONSOLE_SERIAL_19200)) UpdData->SerialPortBaudRate = 9; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_38400)) + else if (CONFIG(CONSOLE_SERIAL_38400)) UpdData->SerialPortBaudRate = 10; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_57600)) + else if (CONFIG(CONSOLE_SERIAL_57600)) UpdData->SerialPortBaudRate = 11; - else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_115200)) + else if (CONFIG(CONSOLE_SERIAL_115200)) UpdData->SerialPortBaudRate = 12; } - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) UpdData->SerialPortType = 0; UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; @@ -74,19 +74,19 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Memory Down */ - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN)) { + if (CONFIG(FSP_MEMORY_DOWN)) { UpdData->MemDownEnable = 1; - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) UpdData->MemDownCh0Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) UpdData->MemDownCh1Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) + if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) UpdData->MemDownCh1Dimm1SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); } else { @@ -98,7 +98,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Fast Boot */ - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + if (CONFIG(ENABLE_MRC_CACHE)) UpdData->MemFastBoot = 1; else UpdData->MemFastBoot = 0; @@ -106,18 +106,18 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Hyper-Threading */ - if (IS_ENABLED(CONFIG_FSP_HYPERTHREADING)) + if (CONFIG(FSP_HYPERTHREADING)) UpdData->HyperThreading = 1; else UpdData->HyperThreading = 0; /* Enable USB */ - if (IS_ENABLED(CONFIG_FSP_EHCI1_ENABLE)) + if (CONFIG(FSP_EHCI1_ENABLE)) UpdData->Ehci1Enable = 1; else UpdData->Ehci1Enable = 0; - if (IS_ENABLED(CONFIG_FSP_EHCI2_ENABLE)) + if (CONFIG(FSP_EHCI2_ENABLE)) UpdData->Ehci2Enable = 1; else UpdData->Ehci2Enable = 0; @@ -133,7 +133,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fs ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 80795c303e..32429ae236 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -61,7 +61,7 @@ static void setup_gpio_io_address(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); - if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) { + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); @@ -105,7 +105,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 5c0cb7e5ab..5b90bbbdd1 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -228,7 +228,7 @@ static void sc_init(struct device *dev) /* Program Serial IRQ register. */ pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) { + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { /* If SERIRQ have to operate in quiet mode, it should have been run in continuous mode for at least one frame first. Use I/O access to achieve the delay of at least one LPC cycle. */ @@ -263,7 +263,7 @@ void southcluster_enable_dev(struct device *dev) } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.pci.devfn == LPC_DEV_FUNC) @@ -281,7 +281,7 @@ static struct device_operations device_ops = { .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, #endif }; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 967fe284bd..1ad89600c1 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -202,14 +202,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (IS_ENABLED(CONFIG_CHROMEOS)) { + if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; } else diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index d26fa4210d..b76dc4ba37 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -32,7 +32,7 @@ void bootblock_soc_early_init(void) bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c index f02b09027a..e23286c2d2 100644 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ b/src/soc/intel/icelake/bootblock/cpu.c @@ -20,7 +20,7 @@ void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && - IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && + CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index ff4d966079..2d35f5bf39 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -139,7 +139,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0fb0b0ecec..0978ab3dea 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -30,7 +30,7 @@ #include <soc/ramstage.h> #include <string.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -129,7 +129,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index f0ad0e25a0..1539b42108 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (CONFIG(INTEL_GMA_ADD_VBT)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index a9cd748b0c..f556b11514 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,7 +49,7 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c index e195865143..a3bce93a7d 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/lpc.c @@ -220,7 +220,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index faf1b2a6c3..821162e768 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -146,7 +146,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 0c35d722fa..ddf642003f 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -91,7 +91,7 @@ void smihandler_soc_at_finalize(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index d3aa900214..ff5b9b2a52 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -79,7 +79,7 @@ static const struct reg_script mtrr_init[] = { asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) light_sd_led(); bootblock_main_with_timestamp(base_timestamp, NULL, 0); @@ -87,7 +87,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) light_sd_led(); /* Initialize the MTRRs */ @@ -98,18 +98,18 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + if (CONFIG(ENABLE_BUILTIN_HSUART0)) reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + if (CONFIG(ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) light_sd_led(); } void bootblock_soc_init(void) { - if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) + if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) light_sd_led(); display_mtrrs(); diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index 67d223817d..13a4d63d3c 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -459,7 +459,7 @@ stackless_PCIConfig_Read: esram_init_done: -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +#if CONFIG(ENABLE_DEBUG_LED) sd_led: /* Set the SDIO controller's base address */ @@ -491,7 +491,7 @@ L43: jmp stackless_PCIConfig_Read L44: -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) +#if CONFIG(ENABLE_DEBUG_LED_ESRAM) jmp light_sd_led #endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ #endif /* CONFIG_ENABLE_DEBUG_LED */ diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index a3bfb3bcbb..595c818593 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -67,7 +67,7 @@ static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C write error!\n", status); @@ -76,7 +76,7 @@ static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length, /* Check for timeout */ if (stopwatch_expired(timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C write timeout!\n", status); @@ -142,7 +142,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read error!\n", status); @@ -151,7 +151,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, /* Check for timeout */ if (stopwatch_expired(timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", status); @@ -204,7 +204,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, uint8_t *tx_buffer; int tx_bytes; - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { for (index = 0; index < seg_count;) { if (index == 0) printk(BIOS_ERR, "I2C Start\n"); @@ -283,7 +283,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Return any detected error */ if (data_bytes < 0) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "I2C segment[%d] failed\n", index); @@ -299,7 +299,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Return any detected error */ if (data_bytes < 0) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "I2C segment[%d] failed\n", index); @@ -330,7 +330,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read error!\n", status); @@ -343,7 +343,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, /* Check for timeout */ if (stopwatch_expired(&timeout)) { - if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + if (CONFIG(I2C_DEBUG)) { printk(BIOS_ERR, "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", status); @@ -362,7 +362,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, regs->ic_tar = 0; /* Return the number of bytes transferred */ - if (IS_ENABLED(CONFIG_I2C_DEBUG)) + if (CONFIG(I2C_DEBUG)) printk(BIOS_ERR, "0x%08x: bytes transferred\n", bytes_transferred); return bytes_transferred; diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c index 9f052a31ec..8ad87d2f43 100644 --- a/src/soc/intel/quark/romstage/car.c +++ b/src/soc/intel/quark/romstage/car.c @@ -54,9 +54,9 @@ void car_soc_pre_console_init(void) reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + if (CONFIG(ENABLE_BUILTIN_HSUART0)) reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + if (CONFIG(ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index b8207117fa..d51587143b 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,7 +29,7 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif @@ -57,7 +57,7 @@ car_stage_entry: .Lhlt: xchg %al, %ah mov $POST_DELAY, %dh -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) @@ -67,7 +67,7 @@ car_stage_entry: .flash_delay: outb %al, $0xED loop .flash_delay -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +#if CONFIG(ENABLE_DEBUG_LED) movl $SD_HOST_CTRL, %ebx movb 0(%ebx), %dl xorb $1, %dl diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index c237da5270..31e130a398 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -36,7 +36,7 @@ asmlinkage void *car_stage_c_entry(void) post_code(0x20); console_init(); - if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + if (CONFIG(STORAGE_TEST)) { uint32_t bar; pci_devfn_t dev; uint32_t previous_bar; @@ -132,7 +132,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; /* Display the ESRAM layout */ - if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { + if (CONFIG(DISPLAY_ESRAM_LAYOUT)) { printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); printk(BIOS_SPEW, "+-------------------+ 0x80080000 - ESRAM end\n"); @@ -175,7 +175,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) upd->RmuLength = rmu_data_len; upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; upd->SocWrRonVal = config->SocWrRonVal; diff --git a/src/soc/intel/quark/sd.c b/src/soc/intel/quark/sd.c index c10ac4fbf1..08db791ffd 100644 --- a/src/soc/intel/quark/sd.c +++ b/src/soc/intel/quark/sd.c @@ -23,7 +23,7 @@ static void init(struct device *dev) { /* Run the SD test */ - if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + if (CONFIG(STORAGE_TEST)) { uint32_t bar; uint32_t previous_bar; uint16_t previous_command; diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 36819a4700..79901f29ff 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -27,7 +27,7 @@ #include <soc/storage_test.h> #include <string.h> -#if IS_ENABLED(CONFIG_STORAGE_LOG) +#if CONFIG(STORAGE_LOG) struct log_entry log[LOG_ENTRIES] CAR_GLOBAL; uint8_t log_index CAR_GLOBAL; int log_full CAR_GLOBAL; @@ -37,7 +37,7 @@ long log_start_time CAR_GLOBAL; static uint8_t drivers_storage[256] CAR_GLOBAL; #define STORAGE_DEBUG BIOS_DEBUG -#define LOG_DEBUG (IS_ENABLED(CONFIG_STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) +#define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) #ifdef __SIMPLE_DEVICE__ uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar, @@ -88,7 +88,7 @@ void storage_test_complete(struct device *dev, uint32_t previous_bar, static void display_log(void) { /* Determine the array bounds */ - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { long delta; uint8_t end; uint8_t index; @@ -121,7 +121,7 @@ static void display_log(void) void sdhc_log_command(struct mmc_command *cmd) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { timer_monotonic_get(&log[log_index].time); log[log_index].cmd = *cmd; log[log_index].cmd_issued = 0; @@ -133,7 +133,7 @@ void sdhc_log_command(struct mmc_command *cmd) void sdhc_log_command_issued(void) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].cmd_issued = 1; } } @@ -142,7 +142,7 @@ void sdhc_log_response(uint32_t entries, uint32_t *response) { unsigned int entry; - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].response_entries = entries; for (entry = 0; entry < entries; entry++) log[log_index].response[entry] = response[entry]; @@ -151,7 +151,7 @@ void sdhc_log_response(uint32_t entries, uint32_t *response) void sdhc_log_ret(int ret) { - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log[log_index].ret = ret; if (++log_index == 0) log_full = 1; @@ -189,7 +189,7 @@ void storage_test(uint32_t bar, int full_initialization) storage_display_setup(media); } else { /* Initialize the log */ - if (IS_ENABLED(CONFIG_STORAGE_LOG)) { + if (CONFIG(STORAGE_LOG)) { log_index = 0; log_full = 0; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 53e6b3c0a8..26a131ddc2 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -182,15 +182,15 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -207,7 +207,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } @@ -275,7 +275,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - if (!IS_ENABLED(CONFIG_NO_FADT_8042)) + if (!CONFIG(NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index ebf4289218..8788bd3e93 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -78,7 +78,7 @@ Device (GPIO) */ Method (GADD, 1, NotSerialized) { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0c4decc186..0aba2e7542 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -74,6 +74,6 @@ Method (_OSC, 4) } /* SGX */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index e766fd767f..ad68ef90cf 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -112,7 +112,7 @@ Device (EMMC) } } -#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE) +#if !CONFIG(EXCLUDE_NATIVE_SD_INTERFACE) Device (SDXC) { Name (_ADR, 0x001E0006) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index acf25ffd48..4358fba40f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -32,14 +32,14 @@ void bootblock_soc_early_init(void) bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } void bootblock_soc_init(void) { /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) bootblock_fsp_temp_ram_init(); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 34cc713124..0f6c8a85d4 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -71,7 +71,7 @@ static void soc_config_acpibase(void) */ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); else pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0); @@ -105,7 +105,7 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEA, ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); @@ -131,7 +131,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1f32a3efa2..98e5baf483 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -60,7 +60,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -68,7 +68,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e43aa833f4..15eb6b2651 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -194,7 +194,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -205,7 +205,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; @@ -323,7 +323,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; - params->CpuConfig.Bits.VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 910dcb88c9..0ff5a137c6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -489,7 +489,7 @@ static void post_mp_init(void) smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) smm_lock(); #endif diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 4da705da73..3d66fa4602 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -41,7 +41,7 @@ static const struct pad_group skl_community_com0_groups[] = { static const struct pad_group skl_community_com1_groups[] = { INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */ -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */ @@ -54,7 +54,7 @@ static const struct pad_group skl_community_com1_groups[] = { }; static const struct pad_group skl_community_com3_groups[] = { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ @@ -86,7 +86,7 @@ static const struct pad_community skl_gpio_communities[] = { }, { .port = PID_GPIOCOM1, .first_pad = GPP_C0, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, #else .last_pad = GPP_E23, @@ -105,7 +105,7 @@ static const struct pad_community skl_gpio_communities[] = { .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -159,7 +159,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { GPP_E, GPP_E}, { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, #endif @@ -172,7 +172,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 1bf6ba410c..07ee67ab88 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -59,9 +59,9 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select another * Kconfig to perform GFX initialization. */ - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) { + if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ - } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); @@ -101,7 +101,7 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (!CONFIG(INTEL_GMA_ADD_VBT)) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index f5065148d3..74328b217e 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -18,7 +18,7 @@ #include <intelblocks/systemagent.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/bootblock.h> #else static inline void bootblock_fsp_temp_ram_init(void) {} diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 137b37e613..1c143a2c43 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -18,7 +18,7 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> #else # include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 24bc2a8c1d..615edac097 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -173,7 +173,7 @@ struct chipset_power_state { * This is used only in FSP1_1 as we wanted to keep the flow unchanged. * Internally fill_power_state calls the new pmc_fill_power_state now */ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 8195440952..72992d2517 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,7 +48,7 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 064ec3118f..465e248700 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -19,7 +19,7 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/soc_binding.h> #else #include <fsp/api.h> @@ -69,7 +69,7 @@ struct vr_config { #define VR_CFG_AMP(i) ((i) * 4) -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 63ff18d406..f7aa584f37 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -239,7 +239,7 @@ static void print_me_version(void *unused) * Print ME version only if UART debugging is enabled. Else, it takes ~1 * second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; hfs.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index bca151e522..60a7070408 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -31,7 +31,7 @@ size_t mmap_region_granularity(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) /* Align to TSEG size when SMM is in use */ if (CONFIG_SMM_TSEG_SIZE != 0) return CONFIG_SMM_TSEG_SIZE; @@ -142,7 +142,7 @@ static size_t get_prmrr_size(uintptr_t dram_base, uintptr_t prmrr_base = dram_base; size_t prmrr_size; - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) prmrr_size = 1*MiB; else prmrr_size = config->PrmrrSize; @@ -186,7 +186,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 9482456922..ee04f0272d 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -28,7 +28,7 @@ car_stage_entry: .Lhlt: xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e147f0c0aa..dc9c528c06 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -88,7 +88,7 @@ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c1a0b97cb2..43ba9c9c6f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -166,7 +166,7 @@ asmlinkage void car_stage_entry(void) top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -225,7 +225,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->Rmt; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) @@ -281,7 +281,7 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index e402ba5e8d..2e93075f7b 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,7 +27,7 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 89169d0e7c..905154e8ac 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -127,7 +127,7 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) [VR_RING] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -240,7 +240,7 @@ void fill_vr_domain_config(void *params, vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) +#if CONFIG(PLATFORM_USES_FSP2_0) vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 3f8e149727..2d998947bb 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -70,7 +70,7 @@ static struct mtk_i2c i2c[7] = { #define I2CTAG "[I2C][PL] " -#if IS_ENABLED(CONFIG_DEBUG_I2C) +#if CONFIG(DEBUG_I2C) #define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) #else #define I2CLOG(fmt, arg...) diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 8d449f7950..041cfaa76f 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -178,7 +178,7 @@ void dramk_check_dq_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32 void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); -#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#if CONFIG(DEBUG_DRAM) #define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg_msg(_x_...) diff --git a/src/soc/mediatek/mt8173/memory.c b/src/soc/mediatek/mt8173/memory.c index 066b18ba48..f17f793cae 100644 --- a/src/soc/mediatek/mt8173/memory.c +++ b/src/soc/mediatek/mt8173/memory.c @@ -32,7 +32,7 @@ void mt_mem_init(const struct mt8173_sdram_params *sdram_params) /* memory calibration */ mt_set_emi(sdram_params); - if (IS_ENABLED(CONFIG_MEMORY_TEST)) { + if (CONFIG(MEMORY_TEST)) { /* * do memory test: * set memory scan range 0x2000 diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 65790d3823..2656d7252d 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -20,7 +20,7 @@ #include <soc/pmic_wrap.h> #include <types.h> -#if IS_ENABLED(CONFIG_DEBUG_PMIC) +#if CONFIG(DEBUG_PMIC) #define DEBUG_PMIC(level, x...) printk(level, x) #else #define DEBUG_PMIC(level, x...) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 04bb2bb28e..781443a397 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -21,7 +21,7 @@ #include <console/console.h> #define dramc_show(_x_...) printk(BIOS_INFO, _x_) -#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg(_x_...) diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 5702b14a01..b2c744198b 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -26,7 +26,7 @@ void mt_mem_init(const struct sdram_params *params) /* memory calibration */ mt_set_emi(params); - if (IS_ENABLED(CONFIG_MEMORY_TEST)) { + if (CONFIG(MEMORY_TEST)) { size_t r; u8 *addr = _dram; diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index cc1e284b66..ce46e5ee35 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -43,7 +43,7 @@ static void enable_cpu_power_partitions(void) power_ungate_partition(POWER_PARTID_C0NC); power_ungate_partition(POWER_PARTID_CE0); - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) { + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) { /* * Deassert reset signal of all the secondary CPUs. * PMC and flow controller will take over the power sequence diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h index fc30481326..e35b582fa2 100644 --- a/src/soc/nvidia/tegra210/include/soc/console_uart.h +++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h @@ -29,19 +29,19 @@ enum console_uart_id { static inline enum console_uart_id console_uart_get_id(void) { - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTA)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTA)) return UART_ID_A; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTB)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTB)) return UART_ID_B; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTC)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTC)) return UART_ID_C; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTD)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTD)) return UART_ID_D; - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTE)) + if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTE)) return UART_ID_E; return UART_ID_NONE; diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index ca369ad3cf..df13cc4f77 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -18,7 +18,7 @@ #include <boot/coreboot_tables.h> -#if IS_ENABLED(CONFIG_HAVE_MTC) +#if CONFIG(HAVE_MTC) int tegra210_run_mtc(void); void soc_add_mtc(struct lb_header *header); diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 213d69d6ba..bfa3c0afb4 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -43,7 +43,7 @@ void romstage(void) printk(BIOS_INFO, "T210: romstage here\n"); -#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT) +#if CONFIG(BOOTROM_SDRAM_INIT) printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index b8359987f9..a9d6835b3a 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -78,7 +78,7 @@ static void enable_tegra210_dev(struct device *dev) if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) return; if (display_init_required()) diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 90edd11cfb..eb3731b7f7 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -54,7 +54,7 @@ static const uart_params_t uart_board_param = { .blsp_uart = BLSP1_UART1, .dbg_uart_gpio = { { -#if IS_ENABLED(CONFIG_IPQ_QFN_PART) +#if CONFIG(IPQ_QFN_PART) .gpio = 60, .func = 2, #else /* bga */ @@ -66,7 +66,7 @@ static const uart_params_t uart_board_param = { .enable = GPIO_ENABLE }, { -#if IS_ENABLED(CONFIG_IPQ_QFN_PART) +#if CONFIG(IPQ_QFN_PART) .gpio = 61, .func = 2, #else /* bga */ diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index bb85acf8cc..fa0990b10b 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -30,7 +30,7 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); - if (is_pmu_gpio(gpio) && IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288)) + if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), pull_val << (gpio.idx * 2)); else diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index 2ac4bfcdce..e4045a8937 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -67,7 +67,7 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) { unsigned long period, duty; -#if IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288) +#if CONFIG(SOC_ROCKCHIP_RK3288) /*use rk pwm*/ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0)); #endif diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 586eaf0d12..5252232f39 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -660,7 +660,7 @@ void rkclk_configure_ddr(unsigned int hz) } rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); - if (IS_ENABLED(CONFIG_RK3399_SPREAD_SPECTRUM_DDR)) + if (CONFIG(RK3399_SPREAD_SPECTRUM_DDR)) rkclk_set_dpllssc(&dpll_cfg); } diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 6e5e1a7f96..65b791d5a3 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -49,7 +49,7 @@ static void soc_init(struct device *dev) */ mmio_resource(dev, 1, (TZRAM_BASE / KiB), (TZRAM_SIZE / KiB)); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) rk_display_init(dev); else printk(BIOS_INFO, "Display initialization disabled.\n"); diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 83e3410ccb..825e35464e 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -58,7 +58,7 @@ Device(SDCN) { Name(_ADR, 0x00140007) } /* end SDCN */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.4 - PCI slot 1, 2, 3 */ Device(PIBR) { @@ -146,7 +146,7 @@ Method(_CRS, 0) { Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#if CONFIG(HUDSON_IMC_FWM) #include "acpi/AmdImc.asl" /* Hudson IMC function */ #endif @@ -175,8 +175,8 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) +#if CONFIG(HUDSON_IMC_FWM) +#if CONFIG(ACPI_ENABLE_THERMAL_ZONE) ITZE() /* enable IMC Fan Control*/ #endif #endif diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index d83b935ffa..cc07565795 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -50,7 +50,7 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -64,7 +64,7 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 148bcccfc9..ee55be174f 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,9 +21,9 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 #endif @@ -51,7 +51,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ @@ -69,7 +69,7 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 7d3ad07205..1b33a0c9c8 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -26,7 +26,7 @@ const char *intr_types[] = { [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" }; -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 230c89f473..28f035c3b8 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -27,7 +27,7 @@ #include "hudson.h" #include "smi.h" -#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE) +#if CONFIG(HUDSON_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) @@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 8ae685e37d..25997d2e9d 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -154,7 +154,7 @@ static void hudson_init_acpi_ports(void) /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { pm_write16(0x6a, ACPI_SMI_CTL_PORT); hudson_enable_acpi_cmd_smi(); } else { @@ -175,8 +175,8 @@ static void hudson_init(void *chip_info) static void hudson_final(void *chip_info) { /* AMD AGESA does not enable thermal zone, so we enable it here. */ - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM) && - !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) + if (CONFIG(HUDSON_IMC_FWM) && + !CONFIG(ACPI_ENABLE_THERMAL_ZONE)) enable_imc_thermal_zone(); } diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 606a529c94..68ff7fb6e3 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -35,7 +35,7 @@ void imc_reg_init(void) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); @@ -43,7 +43,7 @@ void imc_reg_init(void) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) UINT8 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index bf231f8a47..9b18315c5a 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -343,7 +343,7 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index c6528aefba..3406051414 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -68,7 +68,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -101,7 +101,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 4ca29e08c5..8a07565c9a 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -104,7 +104,7 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci1Enable = FALSE; #if DUMP_FCH_SETTING diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index b08e298f06..75ec43997e 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -23,7 +23,7 @@ static void sata_init(struct device *dev) { -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) /************************************** * Configure the SATA port multiplier * **************************************/ diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a1c0755da0..76c587779a 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -36,7 +36,7 @@ #define SPI_REG_CNTRL11 0xd #define CNTRL11_FIFOPTR_MASK 0x07 -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define AMD_SB_SPI_TX_LEN 64 #else #define AMD_SB_SPI_TX_LEN 8 @@ -110,7 +110,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) spi_write(0x1E, 5); spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ spi_write(0x1E, 6); @@ -144,7 +144,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, int chipset_volatile_group_begin(const struct spi_flash *flash) { - if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + if (!CONFIG(HUDSON_IMC_FWM)) return 0; ImcSleep(NULL); @@ -153,7 +153,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash) int chipset_volatile_group_end(const struct spi_flash *flash) { - if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + if (!CONFIG(HUDSON_IMC_FWM)) return 0; ImcWakeup(NULL); diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 5216a105d6..ab48833247 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -99,7 +99,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes, } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) unsigned pm_base; #endif @@ -171,7 +171,7 @@ static void acpi_init(struct device *dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); #endif diff --git a/src/southbridge/amd/amd8111/acpi/sleepstates.asl b/src/southbridge/amd/amd8111/acpi/sleepstates.asl index cb6c53782f..19fde4ded2 100644 --- a/src/southbridge/amd/amd8111/acpi/sleepstates.asl +++ b/src/southbridge/amd/amd8111/acpi/sleepstates.asl @@ -14,7 +14,7 @@ */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) Name (SSFG, 0x05) #else Name (SSFG, 0x01) diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index eab885dd49..469c9368da 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -23,7 +23,7 @@ #include <pc80/isa-dma.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpi.h> #include <arch/acpigen.h> #include <cpu/amd/powernow.h> @@ -131,7 +131,7 @@ static void lpci_set_subsystem(struct device *dev, unsigned int vendor, ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) extern u16 pm_base; @@ -142,7 +142,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) } static void southbridge_acpi_fill_ssdt_generator(struct device *device) { -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) amd_generate_powernow(pm_base + 0x10, 6, 1); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); #endif @@ -160,7 +160,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index b356bf98e6..04b8abcc67 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -49,7 +49,7 @@ typedef union _PCI_ADDR { #endif #define FIXUP_PTR(ptr) ptr -#if IS_ENABLED(CONFIG_SB800_IMC_FWM) +#if CONFIG(SB800_IMC_FWM) #define IMC_ENABLE_OVER_WRITE 0x01 #endif diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index dae8df8288..28b37c30f4 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -100,7 +100,7 @@ static void enable_clocks(void) // change twice. reg32 = *acpi_mmio; reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) -#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK) +#if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK) reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz #endif *acpi_mmio = reg32; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 38a2b76dec..1e1cfe0537 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -163,7 +163,7 @@ static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, @@ -386,9 +386,9 @@ static void sb800_enable(struct device *dev) case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */ /* Initialize the fans */ -#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL) +#if CONFIG(SB800_IMC_FAN_CONTROL) init_sb800_IMC_fans(dev); -#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL) +#elif CONFIG(SB800_MANUAL_FAN_CONTROL) init_sb800_MANUAL_fans(dev); #endif break; diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 90fe8f3697..d6eb1e22b7 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -135,7 +135,7 @@ static void ImcWakeup(void) int chipset_volatile_group_begin(const struct spi_flash *flash) { - if (!IS_ENABLED(CONFIG_SB800_IMC_FWM)) + if (!CONFIG(SB800_IMC_FWM)) return 0; ImcSleep(); @@ -144,7 +144,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash) int chipset_volatile_group_end(const struct spi_flash *flash) { - if (!IS_ENABLED(CONFIG_SB800_IMC_FWM)) + if (!CONFIG(SB800_IMC_FWM)) return 0; ImcWakeup(); diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index e5366e97fc..fc321f8b6b 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -113,7 +113,7 @@ static struct device_operations lpc_ops = { .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, .init = lpc_init, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .scan_bus = scan_lpc_bus, diff --git a/src/southbridge/amd/common/acpi/sleepstates.asl b/src/southbridge/amd/common/acpi/sleepstates.asl index 2f3673878b..21037243f9 100644 --- a/src/southbridge/amd/common/acpi/sleepstates.asl +++ b/src/southbridge/amd/common/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) Name (SSFG, 0x0D) #else Name (SSFG, 0x09) diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 17f5140a71..4e1e7d1856 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -47,7 +47,7 @@ Device(SBUS) { #include "usb.asl" /* 0:14.2 - HD Audio */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #include "audio.asl" #endif @@ -129,7 +129,7 @@ Method(_CRS, 0) { Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#if CONFIG(HUDSON_IMC_FWM) /* TODO: It is unstable. * might be fixed by restructuring */ @@ -161,8 +161,8 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) +#if CONFIG(HUDSON_IMC_FWM) +#if CONFIG(ACPI_ENABLE_THERMAL_ZONE) ITZE() /* enable IMC Fan Control*/ #endif #endif diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index e36c661990..423c48a42a 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -50,8 +50,8 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \ - !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \ + !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -65,8 +65,8 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \ - !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \ + !CONFIG(SOUTHBRIDGE_AMD_PI_KERN) /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 1b5326b88e..448b85e72b 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -63,12 +63,12 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) #define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define FCH_INT_TABLE_SIZE 0x54 #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ @@ -76,7 +76,7 @@ #define PIRQ_GPP3 0x53 /* GPP INT 3 */ #endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #define PIRQ_I2C0 0x70 diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 8061bf7349..fc7a5d1cfd 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -23,13 +23,13 @@ const char *intr_types[] = { [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", [0x7F] = "RSVD\t", -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#elif CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", [0x62] = "GPIO\t", diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 25be669750..abfa897752 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -27,7 +27,7 @@ #include "pci_devs.h" #include <Fch/Fch.h> -#if IS_ENABLED(CONFIG_HUDSON_UART) +#if CONFIG(HUDSON_UART) #include <cpu/x86/msr.h> #include <delay.h> diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 075c577e5e..28e20d38ca 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -27,7 +27,7 @@ #include "hudson.h" #include "smi.h" -#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE) +#if CONFIG(HUDSON_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) @@ -63,7 +63,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; diff --git a/src/southbridge/amd/pi/hudson/gpio.h b/src/southbridge/amd/pi/hudson/gpio.h index dad2279e6c..f07855d765 100644 --- a/src/southbridge/amd/pi/hudson/gpio.h +++ b/src/southbridge/amd/pi/hudson/gpio.h @@ -25,7 +25,7 @@ #define GPIO_OUTPUT_VALUE (1 << 22) #define GPIO_OUTPUT_ENABLE (1 << 23) -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) /* GPIO_0 - GPIO_62 */ #define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500) #define GPIO_0 (GPIO_BANK0_CONTROL + 0x00) @@ -124,7 +124,7 @@ #define GPIO_146 (GPIO_BANK2_CONTROL + 0x48) #define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C) #define GPIO_148 (GPIO_BANK2_CONTROL + 0x50) -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */ +#endif /* CONFIG(SOUTHBRIDGE_AMD_PI_KERN) */ typedef uint32_t gpio_t; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 4db03d8abe..e1ea2ce4b3 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -99,7 +99,7 @@ static void hudson_init_acpi_ports(void) /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT); hudson_enable_acpi_cmd_smi(); } else { @@ -119,9 +119,9 @@ static void hudson_init(void *chip_info) static void hudson_final(void *chip_info) { - if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) { + if (CONFIG(HUDSON_IMC_FWM)) { agesawrapper_fchecfancontrolservice(); - if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) + if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE)) enable_imc_thermal_zone(); } } diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 27ae4edf47..6afcc651e2 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -191,7 +191,7 @@ void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#if IS_ENABLED(CONFIG_HUDSON_UART) +#if CONFIG(HUDSON_UART) void configure_hudson_uart(void); #endif diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 1d504ae598..abb92f29d2 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -86,7 +86,7 @@ static void lpc_init(struct device *dev) /* Set up SERIRQ, enable continuous mode */ byte = (BIT(4) | BIT(7)); - if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) byte |= BIT(6); pm_write8(PM_SERIRQ_CONF, byte); @@ -353,7 +353,7 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 7d4dea2938..579dfaede2 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -71,7 +71,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define IDE_DEV 0x14 #define IDE_FUNC 1 #define IDE_DEVID 0x780C @@ -104,7 +104,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 4268bc2f34..153fe6dea4 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -23,7 +23,7 @@ static void sata_init(struct device *dev) { -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || CONFIG(SOUTHBRIDGE_AMD_PI_KERN) /************************************** * Configure the SATA port multiplier * **************************************/ diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 3c79a81244..17ca98079a 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -342,7 +342,7 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) void rs780_set_tom(struct device *nb_dev) { /* set TOM */ -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); #else diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index cccec44e56..6be6423266 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -105,7 +105,7 @@ static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, } } /* family 10 only, for reg > 0xFF */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -151,7 +151,7 @@ static u8 is_famly10(void) return (cpuid_eax(1) & 0xff00000) != 0; } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; @@ -231,7 +231,7 @@ void rs780_htinit(void) } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + #if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -271,7 +271,7 @@ void rs780_htinit(void) } } -#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if !CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -327,7 +327,7 @@ static void k8_optimization(void) #define k8_optimization() do {} while (0) #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static void fam10_optimization(void) { pci_devfn_t cpu_f0, cpu_f2, cpu_f3; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 8431223690..ca7414a9eb 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -380,7 +380,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* GFX_InitFBAccess finished. */ -#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */ +#if CONFIG(GFXUMA) /* for UMA mode. */ /* GFX_StartMC. */ set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); @@ -442,7 +442,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.sHeader.ucTableFormatRevision = 1; vgainfo.sHeader.ucTableContentRevision = 2; -#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */ +#if !CONFIG(GFXUMA) /* SP mode. */ // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; @@ -627,7 +627,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; @@ -756,7 +756,7 @@ static void rs780_internal_gfx_enable(struct device *dev) struct device *nb_dev = pcidev_on_root(0x0, 0); msr_t sysmem; -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) u32 FB_Start, FB_End; #endif @@ -799,7 +799,7 @@ static void rs780_internal_gfx_enable(struct device *dev) set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f); set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24); -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ struct device *k8_f1 = pcidev_on_root(0x18, 1); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index 6478ade955..fa9433b56b 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -204,7 +204,7 @@ static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev) /* Program Straps. */ romstrap2 = 1 << 26; // enables audio function -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) // bits 7-9: aperture size // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 012a22cd58..222b33df72 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -44,7 +44,7 @@ static void sb700_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5); - if (IS_ENABLED(CONFIG_SPI_FLASH)) + if (CONFIG(SPI_FLASH)) /* Disable decode of variable LPC ROM address ranges 1 and 2. */ reg8 &= ~((1 << 3) | (1 << 4)); else @@ -100,7 +100,7 @@ static void sb700_configure_rom(void) dev = PCI_DEV(0, 0x14, 3); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { + if (CONFIG(SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { uint32_t prev_spi_cfg; volatile uint32_t *spi_mmio; diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index af2b6c1bce..3b801bafe8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -151,7 +151,7 @@ void sb7xx_51xx_lpc_init(void) reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -165,7 +165,7 @@ void sb7xx_51xx_lpc_init(void) // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -404,7 +404,7 @@ static void sb700_devices_por_init(void) printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__); } else { - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { + if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { /* Disable legacy sensor support / reset ASF Slave state machine per RPR 2.27 step 3 */ outb(0x40, SMBUS_AUX_IO_BASE + SMBSLVMISC); } @@ -459,7 +459,7 @@ static void sb700_devices_por_init(void) /*pci_write_config8(dev, 0x79, 0x4F); */ pci_write_config8(dev, 0x78, 0xFF); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { printk(BIOS_DEBUG, "%s: Disabling ISA DMA support\n", __func__); /* Disable LPC ISA DMA Capability */ byte = pci_read_config8(dev, 0x78); @@ -484,7 +484,7 @@ static void sb700_devices_por_init(void) /* LPC Device, BDF:0-20-3 */ printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); } @@ -531,7 +531,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); if (!sata_ahci_mode){ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0); @@ -597,7 +597,7 @@ static void sb700_pmio_por_init(void) uint8_t enable_c_states; enable_c_states = 0; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) if (get_option(&byte, "cpu_c_states") == CB_SUCCESS) enable_c_states = !!byte; #endif @@ -608,7 +608,7 @@ static void sb700_pmio_por_init(void) byte |= 0x20; pmio_write(0x66, byte); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { + if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { /* RPR 2.11 Sx State Settings */ byte = pmio_read(0x65); byte &= ~(1 << 7); /* SpecialFunc = 0 */ @@ -687,7 +687,7 @@ static void sb700_pmio_por_init(void) byte |= 0xc0; pmio_write(0xbb, byte); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* RPR 2.26 Alter CPU reset timing */ byte = pmio_read(0xb2); byte |= 0x1 << 2; /* Enable CPU reset timing option */ @@ -736,7 +736,7 @@ static void sb700_pci_cfg(void) * mentioned in RPR. But I keep them. The registers and the * comments are compatible. */ dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* Enabling LPC DMA function. */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index 94fc5dc4a1..4bc36221ad 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -155,7 +155,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) amd_powernow_update_fadt(fadt); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 2ebd7a59ce..eae8f04e49 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -45,13 +45,13 @@ static void lpc_init(struct device *dev) pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) +#if CONFIG(SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n"); #else isa_dma_init(); #endif - if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { + if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); @@ -66,7 +66,7 @@ static void lpc_init(struct device *dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ @@ -246,7 +246,7 @@ static void sb700_lpc_enable_resources(struct device *dev) sb700_lpc_enable_childrens_resources(dev); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); @@ -275,7 +275,7 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 98b8b6ad77..39aef639d2 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -351,7 +351,7 @@ static void sata_init(struct device *dev) byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 8929f3fdfc..e3594fd583 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -222,7 +222,7 @@ void sb7xx_51xx_enable(struct device *dev) } } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 4c3992d8d5..6b7ce68a1a 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -136,7 +136,7 @@ static void sm_init(struct device *dev) pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ else byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ @@ -305,7 +305,7 @@ static void sm_init(struct device *dev) pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } byte = pci_read_config8(dev, 0xAE); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + if (CONFIG(ENABLE_APIC_EXT_ID)) byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 9805bf6bc1..da653112d7 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -181,7 +181,7 @@ static void usb_init2(struct device *dev) dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) +#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 Erratum 36 */ dword &= ~(1 << 26); if (!ehci_async_data_cache) diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c index eb0ea1c6e0..d94ac73b4a 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -155,7 +155,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; - if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + if (CONFIG(CPU_AMD_MODEL_10XXX)) amd_powernow_update_fadt(fadt); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 4746f153f2..649add5515 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -245,7 +245,7 @@ static struct device_operations lpc_ops = { .read_resources = sb800_lpc_read_resources, .set_resources = sb800_lpc_set_resources, .enable_resources = sb800_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 8671882a9f..b119df287a 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -57,7 +57,7 @@ static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_old, reg; /* family 10 only, for reg > 0xFF */ - if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)) + if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) return; reg = reg_old = pci_read_config32(fam10_dev, reg_pos); @@ -222,7 +222,7 @@ void sr5650_htinit(void) /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -307,7 +307,7 @@ void fam10_optimization(void) msr_t msr; u32 val; - if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)) + if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) return; printk(BIOS_INFO, "fam10_optimization()\n"); diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index f8db2b8c6d..c08809f4aa 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -155,7 +155,7 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { - if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + if (CONFIG(EXT_CONF_SUPPORT)) { printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ } @@ -174,7 +174,7 @@ static void sr5690_set_resources(struct device *dev) { pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ - if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + if (CONFIG(EXT_CONF_SUPPORT)) { uint32_t reg; struct device *amd_ht_cfg_dev; struct device *amd_addr_map_dev; diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 9c72750b90..90ca5641cc 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -808,7 +808,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) struct resource *res; resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; - if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + if (CONFIG(EXT_CONF_SUPPORT)) { res = sr5650_retrieve_cpu_mmio_resource(); if (res) mmconf_base = res->base; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index de6b78c9cb..f22be9ed12 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -79,7 +79,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -724,7 +724,7 @@ static void southbridge_inject_dsdt(struct device *dev) memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); } -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif @@ -915,8 +915,8 @@ static void lpc_final(struct device *dev) RCBA32(0x389c) = spi_opmenu[1]; /* Call SMM finalize() handlers before resume */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || + if (CONFIG(HAVE_SMI_HANDLER)) { + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 58c24784db..5731b9bcd0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -456,7 +456,7 @@ static int mkhi_get_fwcaps(void) } #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -588,7 +588,7 @@ static me_bios_path intel_me_path(struct device *dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -677,7 +677,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index bdd57cdd33..a6ffe896c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -62,7 +62,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -423,7 +423,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -575,7 +575,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -664,7 +664,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -705,7 +705,7 @@ static void intel_me_init(struct device *dev) if (intel_me_read_mbp(&mbp_data)) break; -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5dac57eaf0..67b0d11415 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -47,9 +47,9 @@ #include <southbridge/intel/common/rcba.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) +#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) +#elif CONFIG(SOUTHBRIDGE_INTEL_C216) #define CROS_GPIO_DEVICE_NAME "PantherPoint" #endif diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index e98b8bef7a..6cf4c1061b 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index f1c33b9b06..80c65bb028 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,11 +28,11 @@ void intel_pch_finalize_smm(void) { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || - IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { + if (CONFIG(LOCK_SPI_FLASH_RO) || + CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { int i; u32 lockmask = 1UL << 31; - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) + if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) lockmask |= 1 << 15; for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; @@ -41,7 +41,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ spi_init(); @@ -61,7 +61,7 @@ void intel_pch_finalize_smm(void) pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)) + if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)) /* PMSYNC */ RCBA32_OR(0x33c4, (1UL << 31)); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 7f07a724a3..eb74aa57ce 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -69,13 +69,13 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 #else #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ #define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -86,11 +86,11 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #define GPE0_EN 0x2c #else #define GPE0_EN 0x28 -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index 1f0abeb450..3ee12aa169 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -41,7 +41,7 @@ void sb_rtc_init(void) int rtc_failed = rtc_failure(); if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) elog_add_event(ELOG_TYPE_RTC_RESET); pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 9ae01ad178..4b08c48f27 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -22,7 +22,7 @@ #include "smbus.h" -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else #define dprintk(args...) do {} while (0) @@ -369,8 +369,8 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, /* Only since ICH5 */ static int has_i2c_read_command(void) { - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) || - IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || + CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) return 0; return 1; } diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 40f5412a91..036ac22adc 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -40,7 +40,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) /* Log events from chipset before clearing */ pch_log_state(); @@ -159,7 +159,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) /* Log events from chipset before clearing */ pch_log_state(); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 05b73f20c3..b2cf49a45e 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -136,7 +136,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -244,7 +244,7 @@ em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -316,7 +316,7 @@ static void southbridge_smi_apmc(void) southbridge_finalize_all(); mainboard_finalized = 1; break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -340,7 +340,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif write_pmbase32(PM1_CNT, reg32); @@ -478,7 +478,7 @@ static smi_handler_t southbridge_smi[32] = { * @param node * @param state_save */ -#if IS_ENABLED(CONFIG_SMM_TSEG) +#if CONFIG(SMM_TSEG) void southbridge_smi_handler(void) #else void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a030ff4ef5..bf2a44c86c 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -161,7 +161,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { @@ -283,7 +283,7 @@ void spi_init(void) rcba = pci_read_config32(dev, 0xf0); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020); cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -906,7 +906,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, { ich_spi_controller *cntlr = &g_cntlr; - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); /* Try generic probing first if spi_is_multichip returns 0. */ @@ -963,7 +963,7 @@ static u32 spi_fpr(u32 base, u32 limit) u32 ret; u32 mask, limit_shift; - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { mask = ICH7_SPI_FPR_MASK; limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; } else { @@ -1011,12 +1011,12 @@ static int spi_flash_protect(const struct spi_flash *flash, protect_mask |= SPI_FPR_WPE; break; case READ_PROTECT: - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return -1; protect_mask |= ICH9_SPI_FPR_RPE; break; case READ_WRITE_PROTECT: - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return -1; protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); break; diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 4c5fe96b0d..d60264a15b 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,7 +26,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) u32 class; pci_devfn_t dev; - if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)) + if (!CONFIG(HAVE_USBDEBUG_OPTIONS)) return PCI_DEV(0, 0x1d, 7); if (hcd_idx == 2) diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index e111881581..e0b3cb985c 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <version.h> -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) #include <cpu/x86/smm.h> #endif diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index b93bc09a62..711778e125 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -95,7 +95,7 @@ static void soc_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(struct device *dev) if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 65001cfff1..2891ca4ae7 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -102,7 +102,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 29ed943d3d..4c5e835c7f 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -61,7 +61,7 @@ void soc_enable(struct device *dev); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void soc_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 99400fcbeb..e65576769c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -193,7 +193,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3, }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index b4041ef9e0..00b3866665 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -23,13 +23,13 @@ #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> #include <arch/ioapic.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpi.h> #include <arch/acpigen.h> #endif #include "i82371eb.h" -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) static void enable_intel_82093aa_ioapic(void) { u16 reg16; @@ -85,7 +85,7 @@ static void isa_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -116,7 +116,7 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if IS_ENABLED(CONFIG_IOAPIC) +#if CONFIG(IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -125,7 +125,7 @@ static void sb_read_resources(struct device *dev) #endif } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); @@ -137,7 +137,7 @@ static const struct device_operations isa_ops = { .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a08bbf8d2c..669648ba55 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -330,7 +330,7 @@ static void enable_clock_gating(void) RCBA32(CG) = reg32; } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -445,7 +445,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) i82801gx_lock_smm(dev); #endif @@ -649,7 +649,7 @@ static void lpc_final(struct device *dev) { u16 tco1_cnt; - if (!IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) + if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; SPIBAR16(PREOP) = SPI_OPPREFIX; diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl index d7fb2a56bb..79818a109a 100644 --- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 991ae82259..99078dc402 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -224,7 +224,7 @@ static void i82801ix_init(void *chip_info) i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if !CONFIG(HAVE_SMI_HANDLER) outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ #endif outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index bfa875b74d..421a101bdc 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -28,7 +28,7 @@ #include <southbridge/intel/common/rcba.h> -#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) +#if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) /* * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a * non-conflicting address. No need to worry about speedstep, it diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index db5d3a641a..79a1a1d03f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -370,7 +370,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -394,7 +394,7 @@ static void i82801ix_lock_smm(struct device *dev) /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + if (!CONFIG(PARALLEL_MP)) smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN @@ -466,7 +466,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) i82801ix_lock_smm(dev); #endif } diff --git a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl index d7fb2a56bb..79818a109a 100644 --- a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index d15f0e3556..ec5576d381 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -223,7 +223,7 @@ static void i82801jx_init(void *chip_info) i82801jx_hide_functions(); /* Reset watchdog timer. */ -#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if !CONFIG(HAVE_SMI_HANDLER) outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ #endif outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index f157fa5f61..a365825e7b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -372,7 +372,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) static void i82801jx_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -463,7 +463,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) i82801jx_lock_smm(dev); #endif } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 51b44381de..d440f65eee 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -74,7 +74,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -283,7 +283,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -798,8 +798,8 @@ static void southbridge_fill_ssdt(struct device *device) static void lpc_final(struct device *dev) { /* Call SMM finalize() handlers before resume */ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || + if (CONFIG(HAVE_SMI_HANDLER)) { + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index d774f80f03..df224d364e 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -40,7 +40,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -59,7 +59,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -470,7 +470,7 @@ static me_bios_path intel_me_path(struct device *dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -559,7 +559,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 13579460dc..9b2dd8ac8e 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -62,7 +62,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index d9d021571f..7de8b3b995 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -228,7 +228,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e6e4682057..fabe1c41ba 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -430,7 +430,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -532,7 +532,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -604,7 +604,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -628,7 +628,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a25282a390..90ff02d1f1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -96,7 +96,7 @@ Scope(\) #include "smbus.asl" // Serial IO -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "serialio.asl" #include "lpt_lp.asl" #endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index a5c69e050c..994021c6b0 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -23,7 +23,7 @@ #include "pch.h" #include "chip.h" -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else #include <southbridge/intel/common/gpio.h> @@ -127,7 +127,7 @@ int early_pch_init(const void *gpio_map, pch_enable_bars(); -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) setup_pch_lp_gpios(gpio_map); #else setup_pch_gpios(gpio_map); @@ -150,7 +150,7 @@ int early_pch_init(const void *gpio_map, wake_from_s3 = sleep_type_s3(); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (!wake_from_s3) boot_count_increment(); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 59074e09e6..94b3111d1e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -82,7 +82,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -490,7 +490,7 @@ static void enable_lp_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -754,7 +754,7 @@ static void southbridge_inject_dsdt(struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif @@ -976,7 +976,7 @@ static void lpc_final(struct device *dev) RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; - if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 450091c623..f5f94fe625 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -38,7 +38,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -64,7 +64,7 @@ void intel_me_mbp_clear(pci_devfn_t dev); void intel_me_mbp_clear(struct device *dev); #endif -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -378,7 +378,7 @@ static int mei_recv_msg(void *header, int header_bytes, return mei_wait_for_me_ready(); } -#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) || defined(__SMM__) +#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -480,7 +480,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +536,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -596,7 +596,7 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) +#if CONFIG(ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -723,7 +723,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -812,7 +812,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -851,7 +851,7 @@ static void intel_me_init(struct device *dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -1008,7 +1008,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) host.interrupt_generate = 1; write_host_csr(&host); -#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) +#if !CONFIG(ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1017,7 +1017,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 026fcdd383..97d0aa33b3 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -177,7 +177,7 @@ void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index b14c1f7c91..3c63723f72 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "pch.h" -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #endif diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index cf70d21ad9..426fb4233d 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -28,7 +28,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8c46ab0255..bfa112a807 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -135,13 +135,13 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ -#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) +#if !CONFIG(FINALIZE_USB_ROUTE_XHCI) usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -248,7 +248,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -333,7 +333,7 @@ static void southbridge_smi_apmc(void) case 0xca: usb_xhci_route_all(); break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -352,7 +352,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index bc1e781115..c1670c65a2 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -143,7 +143,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* * Avoid crash (complete with severe memory corruption!) during initial CAR boot * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. @@ -203,7 +203,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, /* SYSCTRL */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if IS_ENABLED(CONFIG_CK804_USE_NIC) +#if CONFIG(CK804_USE_NIC) RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -211,12 +211,12 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if IS_ENABLED(CONFIG_CK804_USE_ACI) +#if CONFIG(CK804_USE_ACI) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif -#if IS_ENABLED(CONFIG_CK804_PCIE_PME_WAKE) +#if CONFIG(CK804_PCIE_PME_WAKE) RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffffffff, 0x00400000, #else RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffbfffff, 0x00000000, @@ -285,7 +285,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), -#if IS_ENABLED(CONFIG_CK804_USE_NIC) +#if CONFIG(CK804_USE_NIC) RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index 6028cd663f..2925b05068 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -22,7 +22,7 @@ #include <arch/acpi.h> #include "chip.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index fe915eecc2..21235548a0 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -297,7 +297,7 @@ static void ck804_lpc_enable_resources(struct device *dev) ck804_lpc_enable_childrens_resources(dev); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { @@ -310,7 +310,7 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, .write_acpi_tables = acpi_write_hpet, #endif @@ -335,7 +335,7 @@ static struct device_operations lpc_slave_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 8944edc376..86ab5b965a 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -24,7 +24,7 @@ #include <delay.h> #include "mcp55.h" -#if IS_ENABLED(CONFIG_MCP55_USE_AZA) +#if CONFIG(MCP55_USE_AZA) #define HDA_ICII_REG 0x68 #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) @@ -203,7 +203,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) static void azalia_init(struct device *dev) { -#if IS_ENABLED(CONFIG_MCP55_USE_AZA) +#if CONFIG(MCP55_USE_AZA) u8 *base; u32 codec_mask, reg32; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 582cb5254e..3099a09599 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -245,7 +245,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, MCP55_DEV(6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, MCP55_DEV(6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, MCP55_DEV(6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* * Avoid crash (complete with severe memory corruption!) during initial CAR boot * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. @@ -257,7 +257,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, MCP55_DEV(1, 0, 0x78), 0xC0FFFFFF, 0x19000000, #endif -#if IS_ENABLED(CONFIG_MCP55_USE_AZA) +#if CONFIG(MCP55_USE_AZA) RES_PCI_IO, MCP55_DEV(6, 1, 0x40), 0x00000000, 0xCB8410DE, #endif @@ -267,7 +267,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, MCP55_MB_SETUP #endif -#if IS_ENABLED(CONFIG_MCP55_USE_AZA) +#if CONFIG(MCP55_USE_AZA) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), @@ -291,7 +291,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, -#if IS_ENABLED(CONFIG_MCP55_USE_NIC) +#if CONFIG(MCP55_USE_NIC) RES_PCI_IO, MCP55_DEV(1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c index 0250900695..4c831ad61d 100644 --- a/src/southbridge/nvidia/mcp55/ht.c +++ b/src/southbridge/nvidia/mcp55/ht.c @@ -24,7 +24,7 @@ #include <arch/acpi.h> #include "mcp55.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) unsigned long acpi_fill_mcfg(unsigned long current) { /* Not implemented */ diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 7e0fc89b69..94ea573020 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -32,7 +32,7 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <stdlib.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) #include <arch/acpigen.h> #endif #include <cpu/amd/powernow.h> @@ -235,7 +235,7 @@ static void mcp55_lpc_enable_resources(struct device *dev) mcp55_lpc_enable_childrens_resources(dev); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void southbridge_acpi_fill_ssdt_generator(struct device *device) { amd_generate_powernow(0, 0, 0); @@ -246,7 +246,7 @@ static struct device_operations lpc_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = mcp55_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, .write_acpi_tables = acpi_write_hpet, #endif @@ -274,7 +274,7 @@ static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 38604389e4..1228d57db2 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -87,7 +87,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) unsigned pm_base; #endif @@ -106,7 +106,7 @@ static void mcp55_sm_read_resources(struct device *dev) static void mcp55_sm_init(struct device *dev) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) struct resource *res; res = find_resource(dev, 0x60); diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index f69273e984..57896e0c01 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -156,7 +156,7 @@ static void fan_smartconfig(const u16 base, const u8 fan, /* 50% duty cycle by default */ const u8 duty = conf->pwm_start ? conf->pwm_start : 50; - if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM)) + if (CONFIG(SUPERIO_ITE_ENV_CTRL_8BIT_PWM)) pwm_start = ITE_EC_FAN_CTL_PWM_DUTY(duty); else pwm_ctrl |= ITE_EC_FAN_CTL_PWM_DUTY(duty); @@ -193,12 +193,12 @@ static void enable_fan(const u16 base, const u8 fan, u8 reg; if (conf->mode == FAN_IGNORE || - (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF) && + (CONFIG(SUPERIO_ITE_ENV_CTRL_NO_ONOFF) && conf->mode <= FAN_MODE_OFF)) return; /* FAN_CTL2 might have its own frequency setting */ - if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) { + if (CONFIG(SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) { reg = ite_ec_read(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); reg &= ~ITE_EC_FAN_PWM_CLOCK_MASK; reg |= ITE_EC_FAN_PWM_DEFAULT_CLOCK; @@ -216,14 +216,14 @@ static void enable_fan(const u16 base, const u8 fan, ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); } - if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { + if (CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { reg = ite_ec_read(base, ITE_EC_FAN_SEC_CTL); if (conf->mode >= FAN_MODE_ON) reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan); @@ -238,7 +238,7 @@ static void enable_fan(const u16 base, const u8 fan, reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); /* Some ITEs have SmartGuardian always enabled */ - if (!IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF)) { + if (!CONFIG(SUPERIO_ITE_ENV_CTRL_NO_ONOFF)) { if (conf->mode >= FAN_SMART_SOFTWARE) reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan); else diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index e67af3445e..e29e33f54a 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -21,7 +21,7 @@ #include "env_ctrl_chip.h" -#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM) +#if CONFIG(SUPERIO_ITE_ENV_CTRL_8BIT_PWM) #define ITE_EC_FAN_MAX_PWM 0xff #define ITE_EC_FAN_PWM_DEFAULT_CLOCK ITE_EC_FAN_PWM_CLOCK_6MHZ #else @@ -58,12 +58,12 @@ #define ITE_EC_FAN_SEC_CTL_TAC_EN(x) (1 << (x)) #define ITE_EC_FAN_TAC_LIMIT(x) \ - (((x) > 3 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) > 3 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0x84 + ((x)-4) * 2) \ : (0x10 + ((x)-1)) \ ) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) \ - (((x) > 3 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) > 3 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0x85 + ((x)-4) * 2) \ : (0x1b + ((x)-1)) \ ) @@ -87,12 +87,12 @@ #define ITE_EC_FAN_CTL_ON(x) (1 << ((x)-1)) #define ITE_EC_FAN_CTL_PWM_CONTROL(x) \ - (((x) > 3 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) > 3 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0x1e + ((x)-4)) \ : (0x15 + ((x)-1)) \ ) -#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CTL_TEMPIN_MASK (7 << 3) #define ITE_EC_FAN_CTL_TEMPIN(x) ((((x)-1) & 7) << 3) #else @@ -145,32 +145,32 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; #define ITE_EC_BEEP_FREQ_DIVISOR(x) (((x) & 0x0f) << 0) #define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa0) \ : (0x60 + ((x)-1) * 8) \ ) #define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa1) \ : (0x61 + ((x)-1) * 8) \ ) #define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa2) \ : (0x62 + ((x)-1) * 8) \ ) #define ITE_EC_FAN_CTL_PWM_START(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa3) \ : (0x63 + ((x)-1) * 8) \ ) #define ITE_EC_FAN_CTL_PWM_AUTO(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa4) \ : (0x64 + ((x)-1) * 8) \ ) #define ITE_EC_FAN_CTL_DELTA_TEMP(x) \ - (((x) == 5 && IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS)) \ + (((x) == 5 && CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS)) \ ? (0xa5) \ : (0x65 + ((x)-1) * 8) \ ) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 68bf5a035f..923bfa3aea 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -21,7 +21,7 @@ #define ITE_EC_TMPIN_CNT 3 -#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CNT 5 #else #define ITE_EC_FAN_CNT 3 diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index c9330e70eb..de1ef0d73e 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -26,7 +26,7 @@ #include "it8716f.h" -#if !IS_ENABLED(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) +#if !CONFIG(SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) void init_ec(u16 base) { diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 9b5c2d3759..b35ec9d8b9 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -64,7 +64,7 @@ void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { nuvoton_pnp_enter_conf_state(dev); - if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A)) + if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route GPIO8 pin group to COM A */ pnp_write_config(dev, 0x2a, 0x40); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 1802193033..c1f557ebed 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -103,7 +103,7 @@ static void npcd378_init(struct device *dev) } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void npcd378_ssdt(struct device *dev) { struct resource *res; @@ -157,7 +157,7 @@ static struct device_operations ops = { .enable = pnp_alt_enable, .init = npcd378_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = npcd378_ssdt, .acpi_name = npcd378_acpi_name, #endif diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c index 3468b6398b..4d7c8dedfc 100644 --- a/src/superio/via/vt1211/superio.c +++ b/src/superio/via/vt1211/superio.c @@ -112,7 +112,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) && IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) +#if CONFIG(CONSOLE_SERIAL) && CONFIG(DRIVERS_UART_8250IO) /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) { diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h index 33a2139c6b..f787014f96 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -8,18 +8,18 @@ #define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_RESUME CONFIG(HAVE_ACPI_RESUME) #else #define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_LATE_RESTORE CONFIG(HAVE_ACPI_RESUME) #define AGESA_ENTRY_INIT_MID TRUE #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE \ - (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \ - IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + (CONFIG(HAVE_ACPI_RESUME) || \ + CONFIG(ENABLE_MRC_CACHE)) #endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c index b4a60a1201..3bf35f1c76 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c @@ -489,7 +489,7 @@ MemPIsIdSupported ( return TRUE; } } - if (IS_ENABLED(CONFIG_FORCE_AM1_SOCKET_SUPPORT)) + if (CONFIG(FORCE_AM1_SOCKET_SUPPORT)) return TRUE; else return FALSE; diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index 51c6b52248..75ba9e7df5 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -916,7 +916,7 @@ fam15_disable_stack_remote_read_exit: # This shouldn't be used with S3 resume IF the stack/cache area is # not reserved and over system memory. #-------------------------------------------------------------------------- -#if !IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if !CONFIG(POSTCAR_STAGE) wbinvd #else invd diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index b9cc39fac5..8f3ca83598 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -651,7 +651,7 @@ fam15_disable_stack_remote_read_exit: # This shouldn't be used with S3 resume IF the stack/cache area is # not reserved and over system memory. #-------------------------------------------------------------------------- -#if !IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if !CONFIG(POSTCAR_STAGE) wbinvd #else invd diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 6c4ad596e1..357b8be6d5 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -615,7 +615,7 @@ fam16_disable_stack_remote_read_exit: # This shouldn't be used with S3 resume IF the stack/cache area is # not reserved and over system memory. #-------------------------------------------------------------------------- -#if !IS_ENABLED(CONFIG_POSTCAR_STAGE) +#if !CONFIG(POSTCAR_STAGE) wbinvd #else invd diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c index 9b2f2e871e..214aa05b24 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram.c @@ -149,9 +149,9 @@ static void bdk_dram_disable_ecc_reporting(bdk_node_t node) static int bdk_libdram_tune_node(int node) { int errs, tot_errs; - int do_dllro_hw = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_HW_OFFSETS); - int do_dllwo = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS); - int do_eccdll = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_ECC_ENABLE); + int do_dllro_hw = CONFIG(CAVIUM_BDK_DDR_TUNE_HW_OFFSETS); + int do_dllwo = CONFIG(CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS); + int do_eccdll = CONFIG(CAVIUM_BDK_DDR_TUNE_ECC_ENABLE); BDK_CSR_INIT(lmc_config, node, BDK_LMCX_CONFIG(0)); // FIXME: probe LMC0 do_eccdll = (lmc_config.s.ecc_ena != 0); // change to ON if ECC enabled diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h index 84f9c3b55a..82b8ea0b11 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h @@ -103,19 +103,19 @@ typedef enum */ #define BDK_TRACE(area, format, ...) do { \ if ((BDK_TRACE_ENABLE_INIT == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_INIT)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_INIT)) || \ (BDK_TRACE_ENABLE_DRAM == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_DRAM)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_DRAM)) || \ (BDK_TRACE_ENABLE_DRAM_TEST == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_DRAM_TEST)) || \ (BDK_TRACE_ENABLE_QLM == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_QLM)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_QLM)) || \ (BDK_TRACE_ENABLE_PCIE_CONFIG == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PCIE_CONFIG)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_PCIE_CONFIG)) || \ (BDK_TRACE_ENABLE_PCIE == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PCIE)) || \ + CONFIG(CAVIUM_BDK_VERBOSE_PCIE)) || \ (BDK_TRACE_ENABLE_PHY == BDK_TRACE_ENABLE_##area && \ - IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PHY))) \ + CONFIG(CAVIUM_BDK_VERBOSE_PHY))) \ printk(BIOS_DEBUG, #area ": " format, ##__VA_ARGS__); \ } while (0) diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 8fd47a6a76..59c4901754 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -14,7 +14,7 @@ */ #include <arch/acpigen.h> -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) #include <gpio.h> #endif #include "chromeos.h" @@ -33,7 +33,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) acpigen_write_integer(gpios[i].type); acpigen_write_integer(gpios[i].polarity); gpio_num = gpios[i].gpio_num; -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) /* Get ACPI pin from GPIO library if available */ if (gpios[i].gpio_num != CROS_GPIO_VIRTUAL) gpio_num = gpio_acpi_pin(gpio_num); diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index d813b22ac0..4852600748 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -15,7 +15,7 @@ #include <security/vboot/vbnv_layout.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* GPIO package generated at run time. */ External (OIPG) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 6831261dc5..6db7fc44dd 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -24,7 +24,7 @@ #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* functions implemented in watchdog.c */ void mark_watchdog_tombstone(void); void reboot_from_watchdog(void); @@ -44,9 +44,9 @@ struct romstage_handoff; #include "gnvs.h" struct device; -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) void chromeos_ram_oops_init(chromeos_acpi_t *chromeos); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC) +#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC) static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ void chromeos_reserve_ram_oops(struct device *dev, int idx); @@ -70,7 +70,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); * ACPI-specific Chrome OS needs. */ void mainboard_chromeos_acpi_generate(void); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) void chromeos_dsdt_generator(struct device *dev); #else #define chromeos_dsdt_generator DEVICE_NOOP diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 660fe2e86f..91a10cb9aa 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -153,7 +153,7 @@ static void enable_update(void *unused) /* clear current post code avoid chatty eventlog on subsequent boot*/ post_code(0); - if (IS_ENABLED(CONFIG_POWER_OFF_ON_CR50_UPDATE)) + if (CONFIG(POWER_OFF_ON_CR50_UPDATE)) poweroff(); halt(); } diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index fbbfd16196..17cb4d9018 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -18,7 +18,7 @@ #include <elog.h> #include <security/vboot/vboot_common.h> -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif @@ -41,7 +41,7 @@ static void elog_add_boot_reason(void *unused) if (dev) { int log_event = 1; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) /* Skip logging developer mode in ACPI resume path */ if (acpi_is_wakeup()) log_event = 0; diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index c72af00c54..7eef2d1338 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -23,7 +23,7 @@ #include <device/device.h> #include "chromeos.h" -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size) { @@ -42,7 +42,7 @@ static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; void *ram_oops; - if (!IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC)) + if (!CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)) return; ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size); @@ -50,7 +50,7 @@ static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) set_ramoops(chromeos, ram_oops, size); } -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC) +#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC) static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {} #else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ @@ -96,7 +96,7 @@ void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) reserve_ram_oops_dynamic(chromeos); } -#elif IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_NON_ACPI) +#elif CONFIG(CHROMEOS_RAMOOPS_NON_ACPI) static void ramoops_alloc(void *arg) { diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 417b9b6744..bbcb211c3a 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -74,7 +74,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) sar_expected_len = buffer_size; bin_buff_adjusted_size = sizeof(struct wifi_sar_limits); - if (!IS_ENABLED(CONFIG_GEO_SAR_ENABLE)) { + if (!CONFIG(GEO_SAR_ENABLE)) { sar_expected_len = buffer_size - sizeof(struct wifi_sar_delta_table) * sizeof(uint8_t) * 2; @@ -88,7 +88,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", wifi_sar_limit_key); - if (!IS_ENABLED(CONFIG_WIFI_SAR_CBFS)) + if (!CONFIG(WIFI_SAR_CBFS)) return -1; printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n"); diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c index d4816e09f9..08e8ddb995 100644 --- a/src/vendorcode/google/chromeos/tpm2.c +++ b/src/vendorcode/google/chromeos/tpm2.c @@ -22,10 +22,10 @@ static void disable_platform_hierarchy(void *unused) { int ret; - if (!IS_ENABLED(CONFIG_TPM2)) + if (!CONFIG(TPM2)) return; - if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) + if (!CONFIG(RESUME_PATH_SAME_AS_BOOT)) return; ret = tlcl_lib_init(); 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