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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-22 16:39:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:02:05 +0000 |
| commit | d13bd05b7a94fc4744cba1a94280797f7c1ce3cd (patch) | |
| tree | 638c43fb19f08a5b883a140fc28a9a0b733e69f9 | |
| parent | 2b79203bdbccb3e807fa59acc9f7b841ca747e69 (diff) | |
| download | coreboot-d13bd05b7a94fc4744cba1a94280797f7c1ce3cd.tar.xz | |
nb/intel: Const'ify pci_devfn_t devices
Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/northbridge/intel/e7505/memmap.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 92b2ae7740..b1ac3d1124 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -12,7 +12,7 @@ void *cbmem_top_chipset(void) { - pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; /* This is at 128 MiB boundary. */ @@ -26,7 +26,7 @@ void northbridge_write_smram(u8 smram); void northbridge_write_smram(u8 smram) { - pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); pci_write_config8(mch, SMRAMC, smram); } diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 422655409a..0d106b8e27 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -33,7 +33,7 @@ void init_iommu() /* clear GTT */ u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); if (gtt & 0x400) { /* VT mode */ - pci_devfn_t igd = PCI_DEV(0, 2, 0); + const pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */ u8 cmd = pci_read_config8(igd, PCI_COMMAND); @@ -52,7 +52,7 @@ void init_iommu() if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; - pci_devfn_t peg = PCI_DEV(0, 1, 0); + const pci_devfn_t peg = PCI_DEV(0, 1, 0); /* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { int val = pci_read_config32(peg, 0xfc) | (1 << 15); |