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authorPatrick Georgi <pgeorgi@chromium.org>2016-04-14 12:35:09 +0200
committerMartin Roth <martinroth@google.com>2016-04-22 17:25:19 +0200
commitd255744dba28565cf61b7318678ccf5f19170028 (patch)
treedc8bda6c41d0e5d4bf808c339f00373cdcf3b57e
parentebef00faf650c7e72da3fdaa0d3ed1fff2e7dce8 (diff)
downloadcoreboot-d255744dba28565cf61b7318678ccf5f19170028.tar.xz
intel/i82801ax: Fix IDE setup console log
Fixes two issues: 1. In (the unlikely) case that dev->chip_info is NULL, the output was depending on an unknown value near the start of the address space. 2. Output for the secondary interface actually printed the primary interface's configuration. Change-Id: Id0f499a85e6e2410b4efd63baf7fffb2fcaa3103 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14361 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/southbridge/intel/i82801ax/ide.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ax/ide.c b/src/southbridge/intel/i82801ax/ide.c
index dcdfe55a64..6fdcacd666 100644
--- a/src/southbridge/intel/i82801ax/ide.c
+++ b/src/southbridge/intel/i82801ax/ide.c
@@ -35,7 +35,7 @@ static void ide_init(struct device *dev)
if (!conf || conf->ide0_enable)
reg16 |= IDE_DECODE_ENABLE;
printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
- conf->ide0_enable ? "on" : "off");
+ (reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
pci_write_config16(dev, IDE_TIM_PRI, reg16);
reg16 = pci_read_config16(dev, IDE_TIM_SEC);
@@ -43,7 +43,7 @@ static void ide_init(struct device *dev)
if (!conf || conf->ide1_enable)
reg16 |= IDE_DECODE_ENABLE;
printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
- conf->ide0_enable ? "on" : "off");
+ (reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
pci_write_config16(dev, IDE_TIM_SEC, reg16);
}