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authorShelley Chen <shchen@chromium.org>2017-05-03 11:24:22 -0700
committerMartin Roth <martinroth@google.com>2017-05-05 22:42:19 +0200
commitd44d0280500d4421601a237a392c488338752825 (patch)
tree384eea22951c7f712f3708e4cfd6a31667444692
parentf49785e8e2ab0fa274d538ba2ecf36881fe4529a (diff)
downloadcoreboot-d44d0280500d4421601a237a392c488338752825.tar.xz
soc/intel/skylake: Enable SATA ports
The current implementation is incorrect and is actually disabling the ports. Fixes that. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19553 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/intel/skylake/sata.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c
index c1104364ff..277d6da246 100644
--- a/src/soc/intel/skylake/sata.c
+++ b/src/soc/intel/skylake/sata.c
@@ -40,14 +40,16 @@ static void *get_ahci_bar(void)
static void sata_final(device_t dev)
{
void *ahcibar = get_ahci_bar();
- u8 port_impl;
+ u32 port_impl, temp;
dev = PCH_DEV_SATA;
/* Read Ports Implemented (GHC_PI) */
- port_impl = read32(ahcibar + 0x0c);
- port_impl = ~port_impl & 0x07;
+ port_impl = read32(ahcibar + 0x0c) & 0x07;
/* Port enable */
- pci_write_config8(dev, 0x92, port_impl);
+ temp = pci_read_config32(dev, 0x92);
+ temp |= port_impl;
+ pci_write_config32(dev, 0x92, temp);
+
}
static struct device_operations sata_ops = {