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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-22 16:10:14 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-27 11:32:37 +0000 |
| commit | db4f3bacce835222e53dea91976b15abc2113779 (patch) | |
| tree | 1fed9f175e7b4c64447f325948c6b19130a43e3b | |
| parent | 49f63e0aa1fa36dd5d7028955beb63b659de075c (diff) | |
| download | coreboot-db4f3bacce835222e53dea91976b15abc2113779.tar.xz | |
sb/amd/cimx/sb800: Const'ify pci_devfn_t devices
Change-Id: I25a6c3ac2426881c6b3f6390ffdc76f08944b7fa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 7a1d05bf17..7181243c94 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -9,9 +9,7 @@ static void enable_rom(void) { u16 word; u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. * BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT29: Port Enable for KBC port 0x60 and 0x64 @@ -43,7 +41,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_s_read_config32(dev, 0xb8); @@ -53,7 +51,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; |