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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:41:06 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:32:10 +0000
commitdddd1cc6913bd0cbb814b68de7315cb84bfb9c2f (patch)
treee4ad63b1db7fbeaf14ad5bf60046a0ed063b86a5
parent7aa3372ce21565962d4cb1090e1f194b6f33f968 (diff)
downloadcoreboot-dddd1cc6913bd0cbb814b68de7315cb84bfb9c2f.tar.xz
src/northbridge: Drop unneeded empty lines
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c1
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c1
-rw-r--r--src/northbridge/amd/pi/00730F01/state_machine.c1
-rw-r--r--src/northbridge/intel/e7505/raminit.c1
-rw-r--r--src/northbridge/intel/gm45/gm45.h5
-rw-r--r--src/northbridge/intel/gm45/pcie.c3
-rw-r--r--src/northbridge/intel/gm45/raminit.c5
-rw-r--r--src/northbridge/intel/haswell/haswell.h1
-rw-r--r--src/northbridge/intel/haswell/report_platform.c1
-rw-r--r--src/northbridge/intel/i945/gma.c2
-rw-r--r--src/northbridge/intel/i945/i945.h2
-rw-r--r--src/northbridge/intel/i945/northbridge.c1
-rw-r--r--src/northbridge/intel/i945/raminit.c2
-rw-r--r--src/northbridge/intel/ironlake/ironlake.h2
-rw-r--r--src/northbridge/intel/pineview/memmap.c1
-rw-r--r--src/northbridge/intel/pineview/raminit.c1
-rw-r--r--src/northbridge/intel/sandybridge/early_dmi.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_tables.h2
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h3
-rw-r--r--src/northbridge/intel/x4x/dq_dqs.c1
-rw-r--r--src/northbridge/intel/x4x/memmap.c1
-rw-r--r--src/northbridge/intel/x4x/raminit.c2
-rw-r--r--src/northbridge/intel/x4x/raminit_ddr23.c2
-rw-r--r--src/northbridge/intel/x4x/raminit_tables.c1
25 files changed, 0 insertions, 44 deletions
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 7c5ecdc8f4..c1e342cde9 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -27,7 +27,6 @@ static struct device *__f2_dev[FX_DEVS];
static struct device *__f4_dev[FX_DEVS];
static unsigned int fx_devs = 0;
-
struct dram_base_mask_t {
u32 base; //[47:27] at [28:8]
u32 mask; //[47:27] at [28:8] and enable at bit 0
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 9d41e7a1f1..207bec2d37 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -543,7 +543,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
return current;
}
-
static struct device_operations northbridge_operations = {
.read_resources = nb_read_resources,
.set_resources = nb_set_resources,
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c
index a97faeb8ea..af1198a001 100644
--- a/src/northbridge/amd/pi/00730F01/state_machine.c
+++ b/src/northbridge/amd/pi/00730F01/state_machine.c
@@ -37,7 +37,6 @@ void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
}
-
void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
{
EmptyHeap();
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index a5280830ea..4822ead662 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -243,7 +243,6 @@ static void mchtest_control(mchtst_cc cmd)
pci_write_config32(MCHDEV, MCHTST, dword);
}
-
/**
*
*/
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index d18b3d42c8..dc993cfb3c 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -170,7 +170,6 @@ enum {
#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
(could be reduced to 10 bytes) */
-
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed14000)
#define DEFAULT_DMIBAR ((u8 *)0xfed18000)
@@ -181,7 +180,6 @@ enum {
#define DEFAULT_EPBAR 0xfed19000
#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
-
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
#define IOMMU_BASE3 0xfed92000
@@ -358,7 +356,6 @@ enum {
#define CxDTAEW(x) (0x1280+(x*0x100))
#define CxDTC(x) (0x1288+(x*0x100))
-
/*
* DMIBAR
*/
@@ -376,7 +373,6 @@ enum {
#define DMILE2D 0x60
#define DMILE2A 0x68
-
/*
* EPBAR
*/
@@ -390,7 +386,6 @@ enum {
#define EPLE1A 0x58
#define EPLE2D 0x60
-
#ifndef __ACPI__
void gm45_early_init(void);
void gm45_early_reset(void);
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 88c3cee117..5a4999e4b0 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -217,7 +217,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29);
}
-
/*\ Setup ASPM on DMI \*/
/* Exit latencies should be checked to be supported by
@@ -232,7 +231,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
DMIBAR8(0x208 + 3) = 0;
DMIBAR32(0x208) &= ~(3 << 20);
-
/*\ Setup ASPM on PEG \*/
/*
* Maybe we just have to advertise ASPM through LCAP[11:10]
@@ -258,7 +256,6 @@ static void setup_rcrb(const int peg_enabled)
/* Link2: link_valid. */
EPBAR8(EPLE2D) |= (1 << 0); /* link valid */
-
/*\ RCRB setup: DMI Port \*/
/* Set component ID of MCH (1). */
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index b95e5631b9..7fc97f01a1 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -216,7 +216,6 @@ void enter_raminit_or_reset(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7));
}
-
/* For a detected DIMM, test the value of an SPD byte to
match the expected value after masking some bits. */
static int test_dimm(sysinfo_t *const sysinfo,
@@ -281,7 +280,6 @@ static void verify_ddr3(sysinfo_t *const sysinfo, int mask)
}
}
-
typedef struct {
int dimm_mask;
struct {
@@ -1710,7 +1708,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Check for bad warm boot. */
reset_on_bad_warmboot();
-
/***** From now on, program according to collected infos: *****/
/* Program DRAM type. */
@@ -1772,10 +1769,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
-
/* Take a breath (the reader). */
-
/* Perform ZQ calibration for DDR3. */
if (sysinfo->spd_type == DDR3)
ddr3_calibrate_zq();
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 44ea9b9858..4bcaaa7728 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -20,7 +20,6 @@
#include "registers/host_bridge.h"
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 8c1b98790c..0b5319bdde 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -78,7 +78,6 @@ static void report_pch_info(void)
int i;
u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
-
const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a4cdf70adf..118d02c32c 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -584,7 +584,6 @@ static u32 freq_to_blc_pwm_ctl(struct device *const dev, u16 pwm_freq)
return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1);
}
-
static void panel_setup(u8 *mmiobase, struct device *const dev)
{
const struct northbridge_intel_i945_config *const conf = dev->chip_info;
@@ -749,7 +748,6 @@ static struct device_operations gma_func0_ops = {
.acpi_name = gma_acpi_name,
};
-
static struct device_operations gma_func1_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 64a945dca4..4b79b2b145 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -87,7 +87,6 @@
#define PEGCC 0x208 /* 32bit */
#define PEGSTS 0x214 /* 32bit */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define IGD_DEV PCI_DEV(0, 2, 0)
@@ -96,7 +95,6 @@
#define BSM 0x5c
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
-
/*
* MCHBAR
*/
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 103b40f831..cfa527f4cc 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -99,7 +99,6 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem);
-
/* The following needs to be 2 lines, otherwise the second
* number is always 0
*/
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 2a8a42bedb..a1a9a9c0b6 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -318,7 +318,6 @@ static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved
printk(BIOS_DEBUG, "only Single Channel Operation.\n");
}
-
for (i = 0; i < (2 * DIMM_SOCKETS); i++) {
int device = get_dimm_spd_address(sysinfo, i), bytes_read;
struct dimm_attr_ddr2_st dimm_info;
@@ -432,7 +431,6 @@ static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved
i, sysinfo->banksize[(i * 2) + 1] * 32);
}
-
sysinfo->rows[i] = dimm_info.row_bits;
sysinfo->cols[i] = dimm_info.col_bits;
sysinfo->banks[i] = dimm_info.banks;
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index aa9a8b7605..7ed6afde3e 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -5,7 +5,6 @@
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
-
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
#define IOMMU_BASE3 0xfed92000
@@ -93,7 +92,6 @@
#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */
#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 146fff2136..bebe3a5b69 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -106,7 +106,6 @@ static uintptr_t northbridge_get_tseg_base(void)
return pci_read_config32(HOST_BRIDGE, TSEG);
}
-
/*
* Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
* As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 43149be723..2248d03c89 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -941,7 +941,6 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8);
}
-
static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk)
{
u8 rank, dq, reg8, j;
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c
index d4cbec8aa7..bcf3e4ce4d 100644
--- a/src/northbridge/intel/sandybridge/early_dmi.c
+++ b/src/northbridge/intel/sandybridge/early_dmi.c
@@ -23,7 +23,6 @@ void early_init_dmi(void)
DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000;
}
-
for (i = 0; i < 2; i++) {
DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000;
}
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index c23a5acff0..326197b9bd 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -300,7 +300,6 @@ static void find_cas_tck(ramctr_timing *ctrl)
ctrl->CAS = val;
}
-
static void dram_timing(ramctr_timing *ctrl)
{
/*
diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h
index 6bf6a1f060..49101cb5ee 100644
--- a/src/northbridge/intel/sandybridge/raminit_tables.h
+++ b/src/northbridge/intel/sandybridge/raminit_tables.h
@@ -23,8 +23,6 @@ extern const u8 frq_aonpd_map[2][8];
extern const u32 frq_comp2_map[2][8];
-
-
extern const u32 pattern[32][16];
extern const u8 use_base[63][32];
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 24360ac110..8f9d118288 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -32,18 +32,15 @@ enum platform_type {
PLATFORM_DESKTOP_SERVER,
};
-
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#include "registers/host_bridge.h"
-
/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */
#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 489340a2bd..7378391507 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -129,7 +129,6 @@ static int decrement_dq_dqs(const struct sysinfo *s,
return CB_SUCCESS;
}
-
#define WT_PATTERN_SIZE 80
static const u32 write_training_schedule[WT_PATTERN_SIZE] = {
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index db0ab9c9fb..aa737f391f 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -104,7 +104,6 @@ static uintptr_t northbridge_get_tseg_base(void)
return pci_read_config32(HOST_BRIDGE, D0F0_TSEG);
}
-
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index a62771d676..c68c70bd31 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -99,7 +99,6 @@ static void select_cas_dramfreq_ddr2(struct sysinfo *s,
try_cas--;
}
-
if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0))
die("Could not find common memory frequency and CAS\n");
@@ -411,7 +410,6 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
return CB_SUCCESS;
}
-
static void select_discrete_timings(struct sysinfo *s,
const struct abs_timings *timings)
{
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 89228f6792..2c250683a1 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -33,7 +33,6 @@ u32 ddr_to_mhz(u32 speed)
return mhz[speed];
}
-
static void program_crossclock(struct sysinfo *s)
{
u8 i, j;
@@ -1283,7 +1282,6 @@ u32 test_address(int channel, int rank)
return channel * 512 * MiB + rank * 128 * MiB;
}
-
/* DDR3 Rank1 Address mirror
* swap the following pins:
* A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index 3cd4879787..e4a80d8441 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -290,7 +290,6 @@ const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
},
};
-
const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
/* 115h[15:0] 117h[23:0] */
{ /* 1N mode */