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authorSeunghwan Kim <sh_.kim@samsung.com>2018-02-01 14:33:04 +0900
committerMartin Roth <martinroth@google.com>2018-03-07 21:16:08 +0000
commitdf2ae96ad8a83fb47d6cdff50353ad28b36ae87a (patch)
treecd2aecb3e3489a5f21c06a25c091c7a2f576d615
parente5372ded417265c2875471f09fdfb0aac005946d (diff)
downloadcoreboot-df2ae96ad8a83fb47d6cdff50353ad28b36ae87a.tar.xz
mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wake
As per the latest schematics, this change configures GPP_B0 as wake source for WLAN. BUG=NONE BRANCH=master TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Reviewed-on: https://review.coreboot.org/23526 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb2
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/gpio.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index fe4e1fa044..6946b38f14 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -381,7 +381,7 @@ chip soc/intel/skylake
end # I2C #4
device pci 1c.0 on
chip drivers/intel/wifi
- register "wake" = "GPE0_PCI_EXP"
+ register "wake" = "GPE0_DW0_00"
device pci 00.0 on end
end
end # PCI Express Port 1
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c
index 72ffc62671..e0b8b7d562 100644
--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c
+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c
@@ -62,8 +62,8 @@ static const struct pad_config gpio_table[] = {
/* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */
PAD_CFG_GPO(GPP_A23, 1, DEEP),
- /* B0 : CORE_VID0 ==> NC(TP721) */
- PAD_CFG_NC(GPP_B0),
+ /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */
+ PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT),
/* B1 : CORE_VID1 ==> NC(TP722) */
PAD_CFG_NC(GPP_B1),
/* B2 : VRALERT# ==> NC */