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| author | Keith Hui <buurin@gmail.com> | 2020-05-05 22:31:59 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-04 07:14:43 +0000 |
| commit | e284bd672c13f3f2d01bcecc62a144fcaa2b4314 (patch) | |
| tree | c9b9d2818851f9930b750863a832b64cc8203033 | |
| parent | 215e7fc399bc75f67209a2ad9ac7c9c2b5a10150 (diff) | |
| download | coreboot-e284bd672c13f3f2d01bcecc62a144fcaa2b4314.tar.xz | |
nb/intel/i440bx: Make ROM area unavailable for MMIO
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 98d06fb8e1..a396a8835d 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -62,6 +62,7 @@ Method(_CRS, 0) { */ MM1B = \_SB.PCI0.NB.TOM1 Local0 = 0x10000000 << 4 + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B Return(TMP) |