bdw refcode: use finalize_usb C code

5 files changed, 119 insertions, 1 deletions

diff --git a/src/soc/intel/broadwell/refcode/Makefile.inc b/src/soc/intel/broadwell/refcode/Makefile.inc
index 3eca45f66d..a6cd5fdbfc 100644
--- a/src/soc/intel/broadwell/refcode/Makefile.inc
+++ b/src/soc/intel/broadwell/refcode/Makefile.inc
@@ -2,6 +2,8 @@ romstage-libs += $(obj)/broadwell_mrc.o
 romstage-y += printk.c
 ramstage-libs += $(obj)/broadwell_refcode.o
 
+ramstage-y += usb.c
+
 $(obj)/%.o: $(src)/soc/intel/broadwell/refcode/%.asm
 	echo "NASM $@"
 	nasm -f elf32 -o $@ $<
diff --git a/src/soc/intel/broadwell/refcode/broadwell_refcode.asm b/src/soc/intel/broadwell/refcode/broadwell_refcode.asm
index 24f3c32753..364bc1a789 100644
--- a/src/soc/intel/broadwell/refcode/broadwell_refcode.asm
+++ b/src/soc/intel/broadwell/refcode/broadwell_refcode.asm
@@ -12,6 +12,8 @@
 bits 32
 global refcode_entry
 
+extern finalize_usb
+
 refcode_entry:
 pushad
 mov eax, dword [esp + 0x24]
@@ -77,7 +79,7 @@ pop edx
 pop ecx
 push dword [eax + 4]
 push eax
-call fcn_000150af  ; call 0x150af
+call finalize_usb
 mov dword [esp], ref_000206c7  ; mov dword [esp], 0x206c7
 call fcn_0001545e  ; call 0x1545e
 add esp, 0x10
diff --git a/src/soc/intel/broadwell/refcode/pch.h b/src/soc/intel/broadwell/refcode/pch.h
new file mode 100644
index 0000000000..ae3a9c60c6
--- /dev/null
+++ b/src/soc/intel/broadwell/refcode/pch.h
@@ -0,0 +1,31 @@
+#ifndef BDW_REFCODE_PCH_H
+#define BDW_REFCODE_PCH_H
+
+#include <device/pci_ops.h>
+
+static inline bool pch_is_lp(void)
+{
+	uint16_t devid = pci_read_config16(PCI_DEV(0,0x1f,0), 2);
+
+	/* WildcatPoint-LP */
+	if (devid >= 0x9cc1 && devid <= 0x9cc9)
+		return true;
+
+	/* LynxPoint-LP */
+	if (devid >= 0x9c41 && devid <= 0x9c45)
+		return true;
+
+	return false;
+}
+
+static inline bool is_wildcat_point_lp(void)
+{
+	uint16_t devid = pci_read_config16(PCI_DEV(0,0x1f,0), 2);
+
+	if (devid >= 0x9cc1 && devid <= 0x9cc9)
+		return true;
+
+	return false;
+}
+
+#endif
diff --git a/src/soc/intel/broadwell/refcode/usb.c b/src/soc/intel/broadwell/refcode/usb.c
new file mode 100644
index 0000000000..818b40a59f
--- /dev/null
+++ b/src/soc/intel/broadwell/refcode/usb.c
@@ -0,0 +1,77 @@
+#define __SIMPLE_DEVICE__ 1
+
+#include <device/pci_ops.h>
+#include <soc/rcba.h>
+#include <soc/iobp.h>
+#include <soc/pci_devs.h>
+#include "pch.h"
+#include "usb.h"
+
+static void finalize_ehci(void)
+{
+	/*
+	if (pch_is_lp()) {
+		if (EHCI dev is disabled) {
+			RCBA32_OR(0x3a84, 5);
+		}
+	}
+	*/
+	pch_iobp_update(0xe5004001,0xffffffff,0xc0);
+
+	// if (EHCI1_DEV is disabled) {
+		//pci_or_config32(EHCI1_DEV, 0xdc, 0x28);
+	//} else {
+		pci_or_config32(PCH_DEV_EHCI, 0xdc, 0x27);
+	//}
+	pci_or_config32(PCH_DEV_EHCI, 0x78, 3);
+
+	/*
+	if (!pch_is_lp()) {
+		if (EHCI2_DEV is disabled) {
+			pci_or_config32(EHCI2_DEV, 0xdc, 0x28);
+		} else {
+			pci_or_config32(EHCI2_DEV, 0xdc, 0x27);
+		}
+		pci_or_config32(EHCI2_DEV, 0x78, 3);
+	}
+	*/
+}
+
+void finalize_usb(void)
+{
+	finalize_ehci();
+
+	pch_iobp_update(0xe5004001,0xffffffff,0xc0);
+
+	uint32_t xhcc = pci_read_config32(PCH_DEV_XHCI, 0x40);
+
+	pci_write_config32(PCH_DEV_XHCI, 0x40, xhcc | 0x100);
+	/* D3IL1E | xHCIL1E | IIL1E >= 1024 bb_cclk */
+	pci_write_config8(PCH_DEV_XHCI, 0x42, ((xhcc >> 16) & 0x7f) | 0x36);
+	pci_or_config16(PCH_DEV_XHCI, 0x44, 0x288);
+
+	uint32_t orval;
+	if (!pch_is_lp()) {
+		orval = 0x40;
+	} else {
+		if (!is_wildcat_point_lp()) {
+			orval = 0x40000;
+		} else {
+			orval = 0x40040;
+		}
+	}
+
+	pci_or_config32(PCH_DEV_XHCI, 0xa0, orval);
+
+	if (!is_wildcat_point_lp()) {
+		if (!pch_is_lp()) {
+			orval = 0;
+		} else {
+			orval = 0x1800;
+		}
+	} else {
+		orval = xhcc;
+	}
+
+	pci_update_config32(PCH_DEV_XHCI, 0xa4, 0xffffdfff, orval);
+}
diff --git a/src/soc/intel/broadwell/refcode/usb.h b/src/soc/intel/broadwell/refcode/usb.h
new file mode 100644
index 0000000000..93cd3e7a8a
--- /dev/null
+++ b/src/soc/intel/broadwell/refcode/usb.h
@@ -0,0 +1,6 @@
+#ifndef BDW_REFCODE_USB_H
+#define BDW_REFCODE_USB_H
+
+void finalize_usb(void);
+
+#endif