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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-09 10:15:21 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-11-12 07:27:00 +0000 |
| commit | fe7367801c3f6f0f876c6258aa924c085e19ed89 (patch) | |
| tree | 7a2dd30fa0db99990efb90e3c14817b58c9eff9b | |
| parent | c27ce827dc788e2c34d72fcc43097d8e858e2f9f (diff) | |
| download | coreboot-fe7367801c3f6f0f876c6258aa924c085e19ed89.tar.xz | |
siemens/mc_apl4: Remove reduced clock rate for I2C0
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index a2a2ba1e8b..8c219af484 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -47,18 +47,6 @@ chip soc/intel/apollolake # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| I2C0 | Proximity Sensor | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_STANDARD - }, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF |