cpu/intel: add IS_ENABLED() around Kconfig symbol references

Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

9 files changed, 13 insertions, 12 deletions

diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index aedd467a9a..be1f28b370 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -316,7 +316,7 @@ static void intel_cores_init(struct device *cpu)
 		       cpu->path.apic.apic_id,
 		       new->path.apic.apic_id);
 
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
 		/* Start the new CPU */
 		if (!start_cpu(new)) {
 			/* Record the error in cpu? */
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 0522f94c9a..57e1bbb30f 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -24,7 +24,7 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
 
-#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
 /* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/lynxpoint/pch.h>
 #else
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ac45ee62ad..c6162dcc84 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -34,7 +34,7 @@
 #include <romstage_handoff.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
 #include "haswell.h"
@@ -182,7 +182,7 @@ void romstage_common(const struct romstage_params *params)
 
 	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
 
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 	/* Ensure the EC is in the right mode for recovery */
 	google_chromeec_early_init();
 #endif
@@ -197,7 +197,7 @@ void romstage_common(const struct romstage_params *params)
 	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
 
 	if (wake_from_s3) {
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 #else
 		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
@@ -239,7 +239,7 @@ void romstage_common(const struct romstage_params *params)
 		/* Save data returned from MRC on non-S3 resumes. */
 		save_mrc_data(params->pei_data);
 	} else if (cbmem_initialize()) {
-	#if CONFIG_HAVE_ACPI_RESUME
+	#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		/* Failed S3 resume, reset to come up cleanly */
 		reset_system();
 	#endif
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 57aa00c007..d9654702e6 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -20,7 +20,7 @@
 #include <smp/spinlock.h>
 #include <assert.h>
 
-#if CONFIG_PARALLEL_CPU_INIT
+#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)
 #error Intel hyper-threading requires serialized CPU init
 #endif
 
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index a57f166d48..ed528d1bdd 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -23,7 +23,7 @@
 
 #include <cpu/intel/microcode/microcode.c>
 
-#if CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
 #include <southbridge/intel/ibexpeak/pch.h>
 #include "model_2065x.h"
 #else
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index fe095c409d..f7e6c1dc91 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -295,7 +295,7 @@ static void intel_cores_init(struct device *cpu)
 		       cpu->path.apic.apic_id,
 		       new->path.apic.apic_id);
 
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
 		/* Start the new CPU */
 		if (!start_cpu(new)) {
 			/* Record the error in cpu? */
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 493d08932c..670b09750e 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -24,7 +24,8 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
-#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
 /* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/bd82x6x/pch.h>
 #else
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 2722454778..589f3b67c6 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -489,7 +489,7 @@ static void intel_cores_init(struct device *cpu)
 		       cpu->path.apic.apic_id,
 		       new->path.apic.apic_id);
 
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
 		/* Start the new CPU */
 		if (!start_cpu(new)) {
 			/* Record the error in cpu? */
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index 3fae3f0bd7..9b9387098c 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -19,7 +19,7 @@
 #include <cpu/x86/msr.h>
 #include <arch/cpu.h>
 
-#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
 static inline int get_global_turbo_state(void)
 {
 	return TURBO_UNKNOWN;