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| author | Furquan Shaikh <furquan@google.com> | 2020-04-28 18:45:20 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-30 20:59:50 +0000 |
| commit | a0284db08df3e0150202fd1cfc8c2c675c19f4de (patch) | |
| tree | de6260608c26aac731c4519f874b7da1b6ea63d7 /AUTHORS | |
| parent | 73716d0e924080ea32274a265a8de04e009c3676 (diff) | |
| download | coreboot-a0284db08df3e0150202fd1cfc8c2c675c19f4de.tar.xz | |
soc/amd/picasso: Introduce enums for SPI read mode and speed
This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions