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author | Julius Werner <jwerner@chromium.org> | 2019-06-06 17:35:25 -0700 |
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committer | Julius Werner <jwerner@chromium.org> | 2019-06-10 18:01:03 +0000 |
commit | 8dcf24fcbf5746693ae0227e9cdfb486efb4907e (patch) | |
tree | cea69a3cc1186b7de5fcab66dfcb54025636049b /COPYING | |
parent | 092fa8bba8c1f6ae0be2afd27b9a113e01b244c8 (diff) | |
download | coreboot-8dcf24fcbf5746693ae0227e9cdfb486efb4907e.tar.xz |
cbfs_spi: Enable speed logging by default for BIOS_DEBUG
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get
in the way (just adding one line per stage, essentially) and should have
no notable overhead. Let's enable it by default for the BIOS_DEBUG log
level rather than having to recompile to get it.
Also fix an issue with building this code on MIPS due to lack of 64-bit
division primitives. (This means MIPS and arm32 board may display
incorrect results when reading more than 4MB in a single transfer, which
sounds very unlikely.)
Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions