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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-08 16:44:39 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-11 16:58:55 +0100 |
| commit | 2e1f73181a770f1c3a8ea5bc1b72bac3732c5c76 (patch) | |
| tree | 002a67ac9623454d957db35b39c791e5130d2e96 /COPYING | |
| parent | 50583f0e1f82f6863762c75acf01c26e163bf2da (diff) | |
| download | coreboot-2e1f73181a770f1c3a8ea5bc1b72bac3732c5c76.tar.xz | |
nb/amd/mct_ddr3: Require minumum training quality for both read and write
The existing MCT code proceeded to the next DRAM training phase if
the minimum lane quality standard passed for either the read or
write direction. Ensure that both pass for a given set of delay
values before proceeding to the next training phase.
Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13993
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions