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| author | Martin Roth <martinroth@google.com> | 2017-06-03 20:16:01 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-12 04:06:40 +0200 |
| commit | 4b18a922f0ab597fc010beeef01cee332fd48705 (patch) | |
| tree | 6f1645f1f8464f1037449ae991c08d257784b444 /Documentation/AMD-S3.txt | |
| parent | 1318ea600b348cff43a66ffa6296a552b59e8888 (diff) | |
| download | coreboot-4b18a922f0ab597fc010beeef01cee332fd48705.tar.xz | |
Documentation: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Unfortunately, some external websites and projects are spelling coreboot
with an uppercase C, so references to those pages can't be changed
without breaking the link.
Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'Documentation/AMD-S3.txt')
| -rw-r--r-- | Documentation/AMD-S3.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/Documentation/AMD-S3.txt b/Documentation/AMD-S3.txt index 48d4c8f3e7..bfabcbe29d 100644 --- a/Documentation/AMD-S3.txt +++ b/Documentation/AMD-S3.txt @@ -13,7 +13,7 @@ /_/ \_\_| |_|_____/ |_____/ |____/ - S3 in Coreboot (V 1.2) + S3 in coreboot (V 1.2) ---------------------------------------- Zheng Bao <zheng.bao@amd.com> @@ -78,7 +78,7 @@ as reserved in e820, or BIOS saves the content into reserved space. Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. 00000000 --- 00100000 BIOS Reserved area. 00100000 --- 00200000 Free -00200000 --- 01000000 Coreboot ramstage area. +00200000 --- 01000000 coreboot ramstage area. 01000000 --- 2e160000 Free 2e160000 --- 2e170000 ACPI table 2e170000 --- 2ef70000 OSRAM @@ -99,7 +99,7 @@ board.[2] Provided by Southbridge vendor code. Early is called before PCI enumeration, and Late is called after that. -Lifecycle of booting, sleeping and waking Coreboot and Ubuntu +Lifecycle of booting, sleeping and waking coreboot and Ubuntu ============================================================= 1. Cold boot. For a system with S3 feature, the BIOS needs to save some data to @@ -130,7 +130,7 @@ when system wakeups. As we mentioned, Firmware detects the SLP_TYPx to find out if the board wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called as they are during cold boot. AmdInitResume and AmdS3LateRestore are -called only during resume. For whole ramstage, Coreboot goes through +called only during resume. For whole ramstage, coreboot goes through almost the same way as cold boot, other than not calling the AmdInitMid, AmdInitLate and AmdS3Save, and restoring all the MTRRs. At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, @@ -141,13 +141,13 @@ When Linux resumes, all the sleeping scripts call their resume hooks. If we are more lucky, all the scripts can go through. More chances that the 99video hangs or fails to get the display back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in -Coreboot/Kconfig. That needs more troubleshooting. +coreboot/Kconfig. That needs more troubleshooting. Reference ========= [1] ACPI40a, http://www.acpi.info/spec40a.htm -[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ -[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c -[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c -[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c +[2] coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ +[3] coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c +[4] coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c +[5] coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c |