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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-01 23:58:59 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-10 20:00:56 +0100 |
| commit | 1f780994ebb7b89cf9e47e7bb9533395b8f4dad0 (patch) | |
| tree | 14c5a82c2462eca0513255da5eed93edc1bc7616 /Documentation/CorebootBuildingGuide.tex | |
| parent | 453b54371681f8810ed50b41efbd7e09dc0f63d6 (diff) | |
| download | coreboot-1f780994ebb7b89cf9e47e7bb9533395b8f4dad0.tar.xz | |
cpu/amd/car: Add romstage BSP stack overrun detection
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable. There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.
Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'Documentation/CorebootBuildingGuide.tex')
0 files changed, 0 insertions, 0 deletions