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| author | Patrick Rudolph <siro@das-labor.org> | 2018-05-14 19:17:05 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-15 15:48:18 +0000 |
| commit | ebdeb4d07da3fe638b45d68266932045c92bd956 (patch) | |
| tree | f15333ce78189719299432e780f501aacc3b21d9 /Documentation/Intel/NativeRaminit/Sandybridge.md | |
| parent | 5dbe8ee7259d72ddfa2c273e2d8fca70addbf6bc (diff) | |
| download | coreboot-ebdeb4d07da3fe638b45d68266932045c92bd956.tar.xz | |
Documentation/Intel/NativeRaminit: Style fixes
Fix tables and minor markdown bugs.
Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/Intel/NativeRaminit/Sandybridge.md')
| -rw-r--r-- | Documentation/Intel/NativeRaminit/Sandybridge.md | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge.md b/Documentation/Intel/NativeRaminit/Sandybridge.md index 8203106c07..5c83a0dad2 100644 --- a/Documentation/Intel/NativeRaminit/Sandybridge.md +++ b/Documentation/Intel/NativeRaminit/Sandybridge.md @@ -18,16 +18,27 @@ The memory initialization code has to take care of lots of duties: * Error handling ## Definitions +```eval_rst ++---------+-------------------------------------------------------------------+------------+--------------+ | Symbol | Description | Units | Valid region | -|---------|-------------------------------------------------------------------|------------|--------------| -| SCK | DRAM system clock cycle time | s | - | -| tCK | DRAM system clock cycle time | 1/256th ns | - | -| DCK | Data clock cycle time: The time between two SCK clock edges | s | - | ++=========+===================================================================+============+==============+ +| SCK | DRAM system clock cycle time | s | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| tCK | DRAM system clock cycle time | 1/256th ns | | ++---------+-------------------------------------------------------------------+------------+--------------+ +| DCK | Data clock cycle time: The time between two SCK clock edges | s | | ++---------+-------------------------------------------------------------------+------------+--------------+ | timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) | -| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - | ++---------+-------------------------------------------------------------------+------------+--------------+ +| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | | ++---------+-------------------------------------------------------------------+------------+--------------+ | REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 | -| MULT | DRAM PLL multiplier | - | [3-12] | -| XMP | Extreme Memory Profiles | - | - | ++---------+-------------------------------------------------------------------+------------+--------------+ +| MULT | DRAM PLL multiplier | | [3-12] | ++---------+-------------------------------------------------------------------+------------+--------------+ +| XMP | Extreme Memory Profiles | | | ++---------+-------------------------------------------------------------------+------------+--------------+ +``` ## (Inoffical) register documentation - [Sandy Bride - Register documentation](SandyBridge_registers.md) |