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authorPaul Menzel <paulepanter@users.sourceforge.net>2017-06-05 12:33:23 +0200
committerPatrick Georgi <pgeorgi@google.com>2017-06-07 12:04:50 +0200
commita8843dee58d15de6860b682975ee01ee61893670 (patch)
treef26fe56b7ddf2452dadd6a9de88819d789410f91 /Documentation/Intel/development.html
parent619e83045a3dfc189cf12b2f755b7a888c428382 (diff)
downloadcoreboot-a8843dee58d15de6860b682975ee01ee61893670.tar.xz
Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/Intel/development.html')
-rw-r--r--Documentation/Intel/development.html8
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index a2ba2781e0..24b2fa9261 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -170,7 +170,7 @@
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
</td>
<td>FindFSP: POST code 0x90
- (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+ (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
is displayed<br>
Enable: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
@@ -303,7 +303,7 @@
<td>TempRamInit</td>
<td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
<td>FSP binary found: POST code 0x90
- (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+ (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
is displayed<br>
TempRamInit successful: POST code
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
@@ -332,7 +332,7 @@
</tr>
<tr>
<td>TempRamExit</td>
- <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+ <td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
<td>Post code 0x91
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
is displayed before calling TempRamExit by
@@ -354,7 +354,7 @@
<td>FspNotify</td>
<td>
The code which calls FspNotify is located in
- src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
+ src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
The fsp_notify_boot_state_callback routine is called three times as specified
by the BOOT_STATE_INIT_ENTRY macros below the routine.
</td>