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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-03 07:28:22 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-05 22:52:46 +0100 |
| commit | e8424cf10f1cd906fb3ece585058925b46ac3704 (patch) | |
| tree | 67b27fbc64a45f0ced7a643630daa0763c776555 /Documentation/Intel/development.html | |
| parent | b251a507140801ed86e43f7f6b88852af07c0d69 (diff) | |
| download | coreboot-e8424cf10f1cd906fb3ece585058925b46ac3704.tar.xz | |
Documentation: Fix links to Intel/documentation.html
Fix links to the documenation.html page which was renamed from
x86Documenation.html.
TEST=Verified documentation links and searched for x86Documenation.html
Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/development.html')
| -rw-r--r-- | Documentation/Intel/development.html | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index b41a8de289..68a52c8c98 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -5,13 +5,13 @@ </head> <body> -<h1>Intel® x86 Coreboot/FSP Development Process</h1> +<h1>Intel® x86 coreboot/FSP Development Process</h1> <p> The x86 development process for coreboot is broken into the following components: </p> <ul> - <li>Coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> - <li>Coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> + <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> + <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> </ul> <p> @@ -22,7 +22,7 @@ <li>Adding coreboot features</li> </ol> -<h2>Minimal Coreboot</h2> +<h2>Minimal coreboot</h2> <p> The combined steps below describe how to bring up a minimal coreboot for a system-on-a-chip (SoC) and a development board: |