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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-04 11:21:33 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-05 22:57:03 +0100 |
| commit | 66decf16446eeb8d3b2da93d0b0086a583bc17bf (patch) | |
| tree | 040939e04a81a15e7f6aa3ffee9eff0cde5792cf /Documentation/Intel/fsp1_1.html | |
| parent | 7e0078b990b7b498391505fb5c492ff7ed8e54cb (diff) | |
| download | coreboot-66decf16446eeb8d3b2da93d0b0086a583bc17bf.tar.xz | |
Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output
TEST=None
Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/fsp1_1.html')
| -rw-r--r-- | Documentation/Intel/fsp1_1.html | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 456db802a8..0727e7ba20 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> + <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li> </ol> <p> @@ -58,6 +59,19 @@ <hr> +<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html>
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