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authorPhilipp Deppenwiese <zaolin@das-labor.org>2018-05-13 15:47:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-05-30 09:14:48 +0000
commit438b463a8f5f739eb02422a3d00b8dfcbeefc2e9 (patch)
treef281339a3f82297a8bb6df61f60331e9e5d45831 /Documentation/Intel
parente462585c9446cecb6f8cf06f62311c6ef18a4cbf (diff)
downloadcoreboot-438b463a8f5f739eb02422a3d00b8dfcbeefc2e9.tar.xz
Documentation: Update index.md and move files
* Add more subdirectories and index.mds. * Move "getting started" and "lessons" into sub-directories. * Move "NativeRaminit" into northbridge/intel/sandybridge folder. * Move "MultiProcessorInit" into soc/intel/icelake folder. * Reference new files Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26262 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Intel')
-rw-r--r--Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md85
-rw-r--r--Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.pngbin123328 -> 0 bytes
-rw-r--r--Documentation/Intel/NativeRaminit/SandyBridge_registers.md2174
-rw-r--r--Documentation/Intel/NativeRaminit/Sandybridge.md135
-rw-r--r--Documentation/Intel/NativeRaminit/Sandybridge_freq.md165
-rw-r--r--Documentation/Intel/NativeRaminit/Sandybridge_read.md153
-rw-r--r--Documentation/Intel/NativeRaminit/timA_lane0-3_adjust_fine.pngbin92363 -> 0 bytes
-rw-r--r--Documentation/Intel/NativeRaminit/timA_lane0-3_discover_420x.pngbin100726 -> 0 bytes
-rw-r--r--Documentation/Intel/NativeRaminit/timA_lane0-3_rt53.pngbin103600 -> 0 bytes
-rw-r--r--Documentation/Intel/NativeRaminit/timA_lane0-3_rt54.pngbin104571 -> 0 bytes
-rw-r--r--Documentation/Intel/NativeRaminit/timA_lane0-3_rt55.pngbin105582 -> 0 bytes
11 files changed, 0 insertions, 2712 deletions
diff --git a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md
deleted file mode 100644
index ab0b5135ed..0000000000
--- a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md
+++ /dev/null
@@ -1,85 +0,0 @@
-# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI
-
-## Introduction
-
-This documentation is intended to document the purpose for creating EFI service
-Interface inside coreboot space to perform CPU feature programming on Application
-Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs.
-
-Today coreboot is capable enough to handle multi-processor initialization on IA platforms.
-
-The multi-processor initialization code has to take care of lots of duties:
-
-1. Bringing all cores out of reset
-2. Load latest microcode on all cores
-3. Sync latest MTRR snapshot between BSP and APs
-4. Perform sets of CPU feature programming
- * CPU Power & Thermal Management
- * Overclocking
- * Intel Trusted Execution Technology
- * Intel Software Guard Extensions
- * Intel Processor Trace etc.
-
-This above CPU feature programming lists are expected to grow with current and future
-CPU complexity and there might be some cases where certain feature programming mightbe
-closed source in nature.
-
-Platform code might need to compromise on those closed source nature of CPU programming
-if we don't plan to provide an alternate interface which can be used by coreboot to
-get-rid of such close source CPU programming.
-
-## Proposal
-
-As coreboot is doing CPU multi-processor initialization for IA platform before FSP-S
-initialization and having all possible information about cores in terms of maximum number
-of cores, APIC ids, stack size etc. It’s also possible for coreboot to extend its own
-support model and create a sets of APIs which later can be used by FSP to run CPU feature
-programming using coreboot published APIs.
-
-Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate
-PPI to perform certain API call, hence coreboot has to created MP services APIs known as
-EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.
-More details here: [PI_Spec_1_6]
-
-### coreboot to publish EFI_MP_SERVICES_PPI APIs
-
-```eval_rst
-+------------------------------+------------------------------------------------------------------+
-| API | Description |
-+==============================+==================================================================+
-| PeiGetNumberOfProcessors | Get the number of CPU's. |
-+------------------------------+------------------------------------------------------------------+
-| PeiGetProcessorInfo | Get information on a specific CPU. |
-+------------------------------+------------------------------------------------------------------+
-| PeiStartupAllAPs | Activate all of the application processors. |
-+------------------------------+------------------------------------------------------------------+
-| PeiStartupThisAP | Activate a specific application processor. |
-+------------------------------+------------------------------------------------------------------+
-| PeiSwitchBSP | Switch the boot strap processor. |
-+------------------------------+------------------------------------------------------------------+
-| PeiEnableDisableAP | Enable or disable an application processor. |
-+------------------------------+------------------------------------------------------------------+
-| PeiWhoAmI | Identify the currently executing processor. |
-+------------------------------+------------------------------------------------------------------+
-```
-
-## Code Flow
-
-Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make
-use of the same to perform some CPU feature programming.
-
-**coreboot-FSP MP init flow**
-![coreboot-fsp mp init flow][coreboot_publish_mp_service_api]
-
-[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png
-
-## Benefits
-1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.
-With proposed model, coreboot will make use of SkipMpInit=0 which will allow to run all
-Silicon recommended CPU programming.
-2. CPU feature programming inside FSP will be more transparent than before as it’s using
-coreboot interfaces to execute those programming.
-3. coreboot will have more control over running those feature programming as API optimization
-handled by coreboot.
-
-[PI_Spec_1_6]: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
diff --git a/Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.png b/Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.png
deleted file mode 100644
index 5836140c53..0000000000
--- a/Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.png
+++ /dev/null
Binary files differ
diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
deleted file mode 100644
index 601157c464..0000000000
--- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
+++ /dev/null
@@ -1,2174 +0,0 @@
-# Inoffical Documentation of Intel MCHBAR register space.
-
-The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device.
-
-This documentation is incomplete and might be incorrect.
-Please handle with care !
-
-**MCHBAR + 0x4**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x10**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x14**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x18**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x1c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x20**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x24**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x28**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x2c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x204**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x210**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x214**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x218**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x21c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x220**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x224**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x228**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x22c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x404**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x410**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x414**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x418**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x41c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x420**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x424**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x428**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x42c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x604**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x610**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x614**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x618**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x61c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x620**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x624**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x628**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x62c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x804**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x810**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x814**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x818**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x81c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x820**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x824**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x828**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x82c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 4
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa04**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa10**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa14**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa18**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa1c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa20**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa24**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa28**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xa2c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 5
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc04**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc10**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc14**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 0:5| Rank 0 CLK phase shift, low |
-+-----------+------------------------------------------------------------------+
-| 6:11| Rank 1 CLK phase shift, low |
-+-----------+------------------------------------------------------------------+
-| 12:17| Rank 2 CLK phase shift, low |
-+-----------+------------------------------------------------------------------+
-| 18:23| Rank 3 CLK phase shift, low |
-+-----------+------------------------------------------------------------------+
-| 24:27| Rankmap to enable clock crossover on |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc18**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 0 | Rank 0 CLK phase shift, high |
-+-----------+------------------------------------------------------------------+
-| 1 | Rank 1 CLK phase shift, high |
-+-----------+------------------------------------------------------------------+
-| 2 | Rank 2 CLK phase shift, high |
-+-----------+------------------------------------------------------------------+
-| 3 | Rank 3 CLK phase shift, high |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc1c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc20**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc24**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc28**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xc2c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 6
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe04**
-
-*Width:* 64 Bit
-
-*Desc:* Lane training result Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:63| Training result, each bit corresponds to one of the 64 settings |
-| | of IO delay |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe10**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe14**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe18**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe1c**
-
-*Width:* 32 Bit
-
-*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 6:11| DQS phase shift on rising edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-| 16:18| IO delay in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20:25| DQS phase shift on falling edge in 1/64 DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe20**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe24**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe28**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0xe2c**
-
-*Width:* 24 Bit
-
-*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 7
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| DQ IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 8:13| DQS IO phase shift in 1/64th DCKs |
-+-----------+------------------------------------------------------------------+
-| 15:17| DQS IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-| 20 | DQ IO phase shift in DCKs |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x1810**
-
-*Width:* 32 Bit
-
-*Desc:* COMP1 Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 9:11| ODT |
-+-----------+------------------------------------------------------------------+
-| 21:23| CLK drive up |
-+-----------+------------------------------------------------------------------+
-| 27:29| CTRL drive up |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x320c**
-
-*Width:* 32 Bit
-
-*Desc:* Command crossover enable Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:5| CLK phase, low |
-+-----------+------------------------------------------------------------------+
-| 12 | CLK phase, high |
-+-----------+------------------------------------------------------------------+
-| 14 | Enable hardware |
-+-----------+------------------------------------------------------------------+
-| 17 | Enable on slot 1 |
-+-----------+------------------------------------------------------------------+
-| 27 | Enable on slot 2 |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x3714**
-
-*Width:* 32 Bit
-
-*Desc:* COMP2 Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| COMP2 value |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4000**
-
-*Width:* 24 Bit
-
-*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:3| tRCD |
-+-----------+------------------------------------------------------------------+
-| 4:7| tRP |
-+-----------+------------------------------------------------------------------+
-| 8:11| CAS |
-+-----------+------------------------------------------------------------------+
-| 12:15| CWL |
-+-----------+------------------------------------------------------------------+
-| 16:19| tRAS |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4004**
-
-*Width:* 32 Bit
-
-*Desc:* TC_RAP - Timing of DDR - Regular Access Parameters Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:3| tRRD |
-+-----------+------------------------------------------------------------------+
-| 4:7| tRTP |
-+-----------+------------------------------------------------------------------+
-| 8:11| CKE |
-+-----------+------------------------------------------------------------------+
-| 12:15| WTR |
-+-----------+------------------------------------------------------------------+
-| 16:19| tFAW |
-+-----------+------------------------------------------------------------------+
-| 24:27| tWR |
-+-----------+------------------------------------------------------------------+
-| 29 | Command 3-state options |
-| | - 0: Drive when channel is active, tri-state when inactive, |
-| | - 1: Always drive command bus |
-+-----------+------------------------------------------------------------------+
-| 30:31| CMD stretch, |
-| | - 00b: 1N, |
-| | - 10b: 2N, |
-| | - 11b: 3N |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x400c**
-
-*Width:* 24 Bit
-
-*Desc:* OTHP ODT control Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:3| tXPDLL ? |
-+-----------+------------------------------------------------------------------+
-| 5:7| tXP ? |
-+-----------+------------------------------------------------------------------+
-| 16:17| ODT stretch |
-+-----------+------------------------------------------------------------------+
-| 18:19| ODT stretch |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x401c**
-
-*Width:* 16 Bit
-
-*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 12:13| ODT stretch |
-+-----------+------------------------------------------------------------------+
-| 14:15| ODT stretch |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4024**
-
-*Width:* 32 Bit
-
-*Desc:* Rounttrip time Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| RTT Rank 0 DIMM 0 |
-+-----------+------------------------------------------------------------------+
-| 8:15| RTT Rank 1 DIMM 0 |
-+-----------+------------------------------------------------------------------+
-| 16:23| RTT Rank 0 DIMM 1 |
-+-----------+------------------------------------------------------------------+
-| 24:31| RTT Rank 1 DIMM 1 |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4028**
-
-*Width:* 24 Bit
-
-*Desc:* SC_IO_LATENCY Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:3| IO latency Rank 0 DIMM 0 |
-+-----------+------------------------------------------------------------------+
-| 4:7| IO latency Rank 1 DIMM 0 |
-+-----------+------------------------------------------------------------------+
-| 8:11| IO latency Rank 0 DIMM 1 |
-+-----------+------------------------------------------------------------------+
-| 12:15| IO latency Rank 1 DIMM 1 |
-+-----------+------------------------------------------------------------------+
-| 16:21| Rount trip - I/O compensation |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4200**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, address Register, Channel 0, queue idx 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| Address |
-+-----------+------------------------------------------------------------------+
-| 20:22| Bank address |
-+-----------+------------------------------------------------------------------+
-| 24:25| Slotrank |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4204**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, address Register, Channel 0, queue idx 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| Address |
-+-----------+------------------------------------------------------------------+
-| 20:22| Bank address |
-+-----------+------------------------------------------------------------------+
-| 24:25| Slotrank |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4208**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, address Register, Channel 0, queue idx 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| Address |
-+-----------+------------------------------------------------------------------+
-| 20:22| Bank address |
-+-----------+------------------------------------------------------------------+
-| 24:25| Slotrank |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x420c**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, address Register, Channel 0, queue idx 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| Address |
-+-----------+------------------------------------------------------------------+
-| 20:22| Bank address |
-+-----------+------------------------------------------------------------------+
-| 24:25| Slotrank |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4220**
-
-*Width:* 8 Bit
-
-*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0 | !RAS |
-+-----------+------------------------------------------------------------------+
-| 1 | !CAS |
-+-----------+------------------------------------------------------------------+
-| 2 | !WE |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4224**
-
-*Width:* 8 Bit
-
-*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0 | !RAS |
-+-----------+------------------------------------------------------------------+
-| 1 | !CAS |
-+-----------+------------------------------------------------------------------+
-| 2 | !WE |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4228**
-
-*Width:* 8 Bit
-
-*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0 | !RAS |
-+-----------+------------------------------------------------------------------+
-| 1 | !CAS |
-+-----------+------------------------------------------------------------------+
-| 2 | !WE |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x422c**
-
-*Width:* 8 Bit
-
-*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0 | !RAS |
-+-----------+------------------------------------------------------------------+
-| 1 | !CAS |
-+-----------+------------------------------------------------------------------+
-| 2 | !WE |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4230**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 16:31| Clock cycles to wait after command |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4234**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 1
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 16:31| Clock cycles to wait after command |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4238**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 2
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 16:31| Clock cycles to wait after command |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x423c**
-
-*Width:* 32 Bit
-
-*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 3
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 16:31| Clock cycles to wait after command |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4284**
-
-*Width:* 24 Bit
-
-*Desc:* RAM training queue, cooldown Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0 | Start executing DRAM command queue |
-+-----------+------------------------------------------------------------------+
-| 16:19| (Number of queued commands - 1) * 4 |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4298**
-
-*Width:* 40 Bit
-
-*Desc:* TC - Refresh parameters Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| tREFI, average period between refresh in DCLK cycles |
-+-----------+------------------------------------------------------------------+
-| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT |
-| | or refresh is allowed in DCLK cycles |
-+-----------+------------------------------------------------------------------+
-| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. |
-| | Should be programmed to 8.9 * tREFI / 1024 |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x42a4**
-
-*Width:* 32 Bit
-
-*Desc:* SRFTP Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:11| tXSDLL |
-+-----------+------------------------------------------------------------------+
-| 12:15| tXS_offset |
-+-----------+------------------------------------------------------------------+
-| 16:25| tZQOPER |
-+-----------+------------------------------------------------------------------+
-| 28:31| tMOD |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4c20**
-
-*Width:* 32 Bit
-
-*Desc:* Scheduler parameters Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| scheduler parameters |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4cb0**
-
-*Width:* 16 Bit
-
-*Desc:* PM - Power-down configuration, Broadcast Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| PDWN_idle_counter, This defines the rank indle period in DCLK |
-| | cycles that causes power-down entrance. The minimum value |
-| | should be greater then or equal to the worst roundtrip time |
-| | plus burst length. |
-+-----------+------------------------------------------------------------------+
-| 8:10| PDWN_mode, selects the mode of power-down: |
-| | - 0x0: No power down, |
-| | - 0x1: APD, |
-| | - 0x2: PPD, |
-| | - 0x3: APD+PPD, |
-| | - 0x4: Reserved, |
-| | - 0x5: Reserved, |
-| | - 0x6: PPD-DLLoff, |
-| | - 0x7: APD+PPD+DLLof |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4e80**
-
-*Width:* 32 Bit
-
-*Desc:* Power mode preset Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| Power mode preset |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4e94**
-
-*Width:* 16 Bit
-
-*Desc:* TC - Refresh parameters Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| OREF_RI, Rank idle period that defines an oppertunity for |
-| | refresh |
-+-----------+------------------------------------------------------------------+
-| 8:11| Refresh_HP_WM, tREFI count level that turns the refresh |
-| | priority to high |
-+-----------+------------------------------------------------------------------+
-| 12:15| Refresh_panic_WM, tREFI count level in which the refresh |
-| | priority is panic |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x4e98**
-
-*Width:* 40 Bit
-
-*Desc:* TC - Refresh parameters Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| tREFI, average period between refresh in DCLK cycles |
-+-----------+------------------------------------------------------------------+
-| 16:24| tRFC, Time of refresh, from beginning of refresh until next ACT |
-| | or refresh is allowed in DCLK cycles |
-+-----------+------------------------------------------------------------------+
-| 25:32| tREFIx9, Maximum time allowed between refreshes to a rank. |
-| | Should be programmed to 8.9 * tREFI / 1024 |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5000**
-
-*Width:* 8 Bit
-
-*Desc:* Global channel size control Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:1| CH_A, defines the largest channel. |
-| | - 00b: Channel 0, |
-| | - 01b: Channel 1, |
-| | - 10b: Channel 2 |
-+-----------+------------------------------------------------------------------+
-| 2:3| CH_B, defines the mid-size channel. |
-| | - 00b: Channel 0, |
-| | - 01b: Channel 1, |
-| | - 10b: Channel 2 |
-+-----------+------------------------------------------------------------------+
-| 2:3| CH_C, defines the smallest channel. |
-| | - 00b: Channel 0, |
-| | - 01b: Channel 1, |
-| | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5004**
-
-*Width:* 32 Bit
-
-*Desc:* Address Decode Register, Channel 0
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| DIMMA size in 256 MB multiples |
-+-----------+------------------------------------------------------------------+
-| 16 | DIMM A select (DAS) Slot to DIMM mapping, |
-| | - 0: DIMMA, DIMMB, |
-| | - 1: DIMMB, DIMMA |
-+-----------+------------------------------------------------------------------+
-| 17 | DIMM A number of ranks |
-+-----------+------------------------------------------------------------------+
-| 19 | DIMM A DRAM width x8 / x16 |
-+-----------+------------------------------------------------------------------+
-| 8:15| DIMM B size in 256 MB multiples |
-+-----------+------------------------------------------------------------------+
-| 18 | DIMM B number of ranks |
-+-----------+------------------------------------------------------------------+
-| 20 | DIMM B DRAM width in 8x / x16 |
-+-----------+------------------------------------------------------------------+
-| 21 | Rank interleave enable |
-+-----------+------------------------------------------------------------------+
-| 22 | Enhanced interleave enable |
-+-----------+------------------------------------------------------------------+
-| 26 | High order Rank interleave enable |
-+-----------+------------------------------------------------------------------+
-| 27:29| High Order Rank interleave Address. Selects on of address bits |
-| | 20-27 to use for high rank interleave |
-+-----------+------------------------------------------------------------------+
-| 24:25| ECC, |
-| | - 00b: No ECC active, |
-| | - 01b: ECC is active on IO, |
-| | - 11b: ECC is active on both IO and ECC logic |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5030**
-
-*Width:* 8 Bit
-
-*Desc:* Global DDR3 control Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 1 | DDR reset |
-+-----------+------------------------------------------------------------------+
-| 2 | DCLK enable |
-+-----------+------------------------------------------------------------------+
-| 5 | IO reset |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5034**
-
-*Width:* 32 Bit
-
-*Desc:* Version Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| MRC version |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5060**
-
-*Width:* 16 Bit
-
-*Desc:* PM - Self refresh config Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:15| Idle_timer, The value is used when the SREF_enable field is set |
-| | and defines the # of cycles that there should not be any |
-| | transaction in order to enter self-refresh. |
-+-----------+------------------------------------------------------------------+
-| 16 | SR_Enable, enable self-refresh mechanism. Clear SREF_en and |
-| | SREF_exit first. |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5084**
-
-*Width:* 24 Bit
-
-*Desc:* RCOMP status Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 16 | Busy |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5090**
-
-*Width:* 32 Bit
-
-*Desc:* ECC - Address compare for ECC error injection Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| Inject error when ECC_Inj_Addr_Compare[31:0] = ADDR[37:6] |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5094**
-
-*Width:* 32 Bit
-
-*Desc:* ECC - Address mask for ECC error injection Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = |
-| | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5e00**
-
-*Width:* 32 Bit
-
-*Desc:* MC_BIOS_REQ Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
-+-----------+------------------------------------------------------------------+
-| 8 | - 1: 100Mhz reference clock |
-| | - 0: 133Mhz reference clock (IvyBridge only) |
-+-----------+------------------------------------------------------------------+
-| 31 | PLL busy |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5e04**
-
-*Width:* 8 Bit
-
-*Desc:* MC_BIOS_DATA Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 0:7| Active multiplier: |
-| | - 100Mhz [7,12], |
-| | - 133Mhz [3,19] |
-+-----------+------------------------------------------------------------------+
-```
-
-**MCHBAR + 0x5f08**
-
-*Width:* 16 Bit
-
-*Desc:* RCOMP control Register
-
-```eval_rst
-+-----------+------------------------------------------------------------------+
-| Bit | Description |
-+===========+==================================================================+
-| 8 | Force RCOMP |
-+-----------+------------------------------------------------------------------+
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge.md b/Documentation/Intel/NativeRaminit/Sandybridge.md
deleted file mode 100644
index 5c83a0dad2..0000000000
--- a/Documentation/Intel/NativeRaminit/Sandybridge.md
+++ /dev/null
@@ -1,135 +0,0 @@
-# Sandy Bridge Raminit
-
-## Introduction
-
-This documentation is intended to document the closed source memory controller
-hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
-
-The memory initialization code has to take care of lots of duties:
-1. Selection of operating frequency
-* Selection of common timings
-* Applying frequency specific compensation values
-* Read training of all populated channels
-* Write training of all populated channels
-* Adjusting delay networks of address and command signals
-* DQS training of all populated channels
-* Programming memory map
-* Report DRAM configuration
-* Error handling
-
-## Definitions
-```eval_rst
-+---------+-------------------------------------------------------------------+------------+--------------+
-| Symbol | Description | Units | Valid region |
-+=========+===================================================================+============+==============+
-| SCK | DRAM system clock cycle time | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| tCK | DRAM system clock cycle time | 1/256th ns | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| MULT | DRAM PLL multiplier | | [3-12] |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| XMP | Extreme Memory Profiles | | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-```
-
-## (Inoffical) register documentation
-- [Sandy Bride - Register documentation](SandyBridge_registers.md)
-
-## Frequency selection
-- [Sandy Bride - Frequency selection](Sandybridge_freq.md)
-
-## Read training
-- [Sandy Bride - Read training](Sandybridge_read.md)
-
-### SMBIOS type 17
-The SMBIOS specification allows to report the memory configuration in use.
-On GNU/Linux you can run `# dmidecode -t 17` to view it.
-Example output of dmidecode:
-
-```
-Handle 0x0045, DMI type 17, 34 bytes
- Memory Device
- Array Handle: 0x0042
- Error Information Handle: Not Provided
- Total Width: 64 bits
- Data Width: 64 bits
- Size: 8192 MB
- Form Factor: DIMM
- Set: None
- Locator: ChannelB-DIMM0
- Bank Locator: BANK 2
- Type: DDR3
- Type Detail: Synchronous
- Speed: 933 MHz
- Manufacturer: 0420
- Serial Number: 00000000
- Asset Tag: 9876543210
- Part Number: F3-1866C9-8GSR
- Rank: 2
- Configured Clock Speed: 933 MHz
-```
-The memory frequency printed by dmidecode is the active memory frequency. It's
-**not** the double datarate and it's **not** the one encoded maximum frequency
-in each DIMM's SPD.
-
-> **Note:** This feature is available since coreboot 4.4
-
-### MRC cache
-The name *MRC cache* might be missleading as in case of *Native ram init*
-there's no MRC, but for historical reasons it's still named *MRC cache*.
-The MRC cache is part of flash memory that is writeable by coreboot.
-At the end of the boot process coreboot will write the RAM training results to
-flash for future use, as RAM training is time intensive. Storing the results
-allows to boot faster on normal boot and allows to support S3 resume,
-as the RAM training results can't be stored in RAM (you need to configure
-the memory controller first to access RAM).
-
-The MRC cache needs to be invalidated in case the memory configuration has
-been changed. To detect a changed memory configuration the CRC16 of each DIMM
-is stored to MRC cache.
-> **Note:** This feature is available since coreboot 4.4
-
-### Error handling
-As of writing the only supported error handling is to disable the failing
-channel and restart the memory training sequence. It's very likely to succeed,
-as memory channels operate independent of each other.
-In case no DIMM could be initilized coreboot will halt. The screen will stay
-black until you power of your device. On some platforms there's additional
-feedback to indicate such an event.
-
-If you find `dmidecode -t 17` to report only half of the memory installed,
-it's likely that a fatal memory init failure had happened.
-It is assumed, that a working board with less physical memory, is much better,
-than a board that doesn't boot at all.
-
-> **Note:** This feature is available since coreboot 4.5
-
-Try to swap memory modules and or try to use a different vendor. If nothing
-helps you could have a look at capter [Debuggin] or report a ticket
-at [ticket.coreboot.org]. Please provide a full RAM init log,
-that has been captured using EHCI debug.
-
-To enable extensive RAM training logging enable the Kconfig option
-`DEBUG_RAM_SETUP`
-#### Lenovo Thinkpads
-Lenovo Thinkpads do have an additional feature to indicate that RAM init has
-failed and coreboot has died (it calls die() on fatal error, thus the name).
-The Kconfig options
-`H8_BEEP_ON_DEATH`
-`H8_FLASH_LEDS_ON_DEATH`
-enable blinking LEDs and enable a beep to indicate death.
-
-> **Note:** This feature is available since coreboot 4.7
-
-## Debugging
-It's recommended to use an external debugger, such as serial or EHCI debug
-dongle. In case of failing memory init the board might not boot at all,
-preventing you from using CBMEM.
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md
deleted file mode 100644
index d8b73b3aec..0000000000
--- a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md
+++ /dev/null
@@ -1,165 +0,0 @@
-# Frequency selection
-
-## Introduction
-This chapter explains the frequency selection done on Sandybride and Ivybridge.
-
-## Definitions
-```eval_rst
-+---------+-------------------------------------------------------------------+------------+--------------+
-| Symbol | Description | Units | Valid region |
-+=========+===================================================================+============+==============+
-| SCK | DRAM system clock cycle time | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| tCK | DRAM system clock cycle time | 1/256th ns | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| MULT | DRAM PLL multiplier | | [3-12] |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| XMP | Extreme Memory Profiles | | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-```
-## SPD
-The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
-located on every DIMM is factory program with various timings. One of them
-specifies the maximum clock frequency the DIMM should be used with. The
-operating frequency is stores as fixed point value (tCK), rounded to the next
-smallest supported operating frequency. Some
-[SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
-contains additional and optional
-[XMP](https://de.wikipedia.org/wiki/Extreme_Memory_Profile "Extreme Memory Profile")
-data, that stores so called "performance" modes, that advertises higher clock
-frequencies.
-
-## XMP profiles
-At time of writing coreboot's raminit is able to parse XMP profile 1 and 2.
-Only **XMP profile 1** is being used in case it advertises:
-* 1.5V operating voltage
-* The channel's installed DIMM count doesn't exceed the XMP coded limit
-
-In case the XMP profile doesn't fullfill those limits, the regular SPD will be
-used.
-> **Note:** XMP Profiles are supported since coreboot 4.4.
-
-It is possible to ignore the max DIMM count limit set by XMP profiles.
-By activating Kconfig option `NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS` it is
-possible to install two DIMMs per channel, even if XMP tells you not to do.
-
-> **Note:** Ignoring XMP Profiles limit is supported since coreboot 4.7.
-
-## Soft fuses
-Every board manufacturer does program "soft" fuses to indicate the maximum
-DRAM frequency supported. However, those fuses don't set a limit in hardware
-and thus are called "soft" fuses, as it is possible to ignore them.
-
-> **Note:** Ignoring the fuses might cause system instability !
-
-On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
-read. coreboot reads those registers and honors the limit in case the Kconfig
-option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
-Power users that want to let their RAM run at DRAM's "stock" frequency need to
-enable the Kconfig symbol.
-
-It is possible to override the soft fuses limit by using a board-specific
-[devicetree](#devicetree) setting.
-
-> **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
-
-## Hard fuses
-"Hard" fuses are programmed by Intel and limit the maximum frequency that can
-be used on a given CPU/board/chipset. At time of writing there's no register
-to read this limit, before trying to set a given DRAM frequency. The memory PLL
-won't lock, indicating that the chosen memory multiplier isn't available. In
-this case coreboot tries the next smaller memory multiplier until the PLL will
-lock.
-
-## Devicetree
-The devicetree register `max_mem_clock_mhz` overrides the "soft" fuses set
-by the board manufacturer.
-
-By using this register it's possible to force a minimum operating frequency.
-
-## Reference clock
-While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
-supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
-multiplier to select the DRAM frequency (SCK) by the following formula:
-
- REFCK * MULT = 1 / DCK
-
-> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
-
-## Sandy Bride's supported frequencies
-```eval_rst
-+------------+-----------+------------------+-------------------------+---------------+
-| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
-+============+===========+==================+=========================+===============+
-| 400 | DDR3-800 | 3 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 533 | DDR3-1066 | 4 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 666 | DDR3-1333 | 5 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 800 | DDR3-1600 | 6 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 933 | DDR3-1866 | 7 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 1066 | DDR3-2166 | 8 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-```
-
-## Ivybridge's supported frequencies
-```eval_rst
-+------------+-----------+------------------+-------------------------+---------------+
-| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
-+============+===========+==================+=========================+===============+
-| 400 | DDR3-800 | 3 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 533 | DDR3-1066 | 4 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 666 | DDR3-1333 | 5 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 800 | DDR3-1600 | 6 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 933 | DDR3-1866 | 7 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 1066 | DDR3-2166 | 8 | 133 MHz | |
-+------------+-----------+------------------+-------------------------+---------------+
-| 700 | DDR3-1400 | 7 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-| 800 | DDR3-1600 | 8 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-| 900 | DDR3-1800 | 9 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-| 1000 | DDR3-2000 | 10 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-| 1100 | DDR3-2200 | 11 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-| 1200 | DDR3-2400 | 12 | 100 MHz | '1 |
-+------------+-----------+------------------+-------------------------+---------------+
-```
-> '1: since coreboot 4.6
-
-## Multiplier selection
-coreboot select the maximum frequency to operate at by the following formula:
-```
-if devicetree's max_mem_clock_mhz > 0:
- freq_max := max_mem_clock_mhz
-else:
- freq_max := soft_fuse_max_mhz
-
-for i in SPDs:
- freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
-```
-
-As you can see, by using DIMMs with different maximum DRAM frequencies, the
-slowest DIMMs' frequency will be selected, to prevent over-clocking it.
-
-The selected frequency gives the PLL multiplier to operate at. In case the PLL
-locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
-all DIMMs. At this point it's not possible to change the multiplier again,
-until the system has been powered off. In case the PLL doesn't lock, the next
-smaller multiplier will be used until a working multiplier will be found.
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge_read.md b/Documentation/Intel/NativeRaminit/Sandybridge_read.md
deleted file mode 100644
index 0496657b3f..0000000000
--- a/Documentation/Intel/NativeRaminit/Sandybridge_read.md
+++ /dev/null
@@ -1,153 +0,0 @@
-# Read training
-
-## Introduction
-
-This chapter explains the read training sequence done on Sandy Bride and
-Ivy Bridge memory initialization.
-
-Read training is done to compensate the skew between DQS and SCK and to find
-the smallest supported roundtrip delay.
-
-Every board does have a vendor depended routing topology, and can be equip
-with any combination of DDR3 memory modules, that introduces different
-skew between the memory lanes. With DDR3 a "Fly-By" routing topology
-has been introduced, that makes the biggest part of DQS-SCK skew.
-The memory code measures the actual skew and actives delay gates,
-that will "compensate" the skew.
-
-When in read training the DRAM and the controller are placed in a special mode.
-On every read instruction the DRAM outputs a predefined pattern and the memory
-controller samples the DQS after a given delay. As the pattern is known, the
-actual delay of every lane can be measured.
-
-The values programmed in read training effect DRAM-to-MC transfers only !
-
-## Definitions
-```eval_rst
-+---------+-------------------------------------------------------------------+------------+--------------+
-| Symbol | Description | Units | Valid region |
-+=========+===================================================================+============+==============+
-| SCK | DRAM system clock cycle time | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| tCK | DRAM system clock cycle time | 1/256th ns | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| MULT | DRAM PLL multiplier | | [3-12] |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| XMP | Extreme Memory Profiles | | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-| DQS | Data Strobe signal used to sample all lane's DQ signals | | |
-+---------+-------------------------------------------------------------------+------------+--------------+
-```
-## Hardware
-The hardware does have delay logic blocks that can delay the DQ / DQS of a
-lane/rank by one or multiple clock cylces and it does have delay logic blocks
-that can delay the signal by a multiple of 1/64th DCK per lane.
-
-All delay values can be controlled via software by writing registers in the
-MCHBAR.
-
-## IO phase
-
-The IO phase can be adjusted in [0-512) * 1/64th DCK. Incrementing it by 64 is
-the same as Incrementing IO delay by 1.
-
-## IO delay
-Delays the DQ / DQS signal by one or multiple clock cycles.
-
-### Roundtrip time
-The roundtrip time is the time the memory controller waits for data arraving
-after a read has been issued. Due to clock-domain crossings, multiple
-delay instances and phase interpolators, the signal runtime to DRAM and back
-to memory controller defaults to 55 DCKs. The real roundtrip time has to be
-measured.
-
-After a read command has been issued, a counter counts down until zero has been
-reached and activates the input buffers.
-
-The following pictures shows the relationship between those three values.
-The picture was generated from 16 IO delay values times 64 timA values.
-The highest IO delay was set on the right-hand side, while the last block
-on the left-hand side has zero IO delay.
-
-#### roundtrip 55 DCKs
-![timA for lane0 - lane3, roundtrip 55][timA_lane0-3_rt55]
-
-[timA_lane0-3_rt55]: timA_lane0-3_rt55.png
-
-#### roundtrip 54 DCKs
-![timA for lane0 - lane3, roundtrip 54][timA_lane0-3_rt54]
-
-[timA_lane0-3_rt54]: timA_lane0-3_rt54.png
-
-
-#### roundtrip 53 DCKs
-![timA for lane0 - lane3, roundtrip 53][timA_lane0-3_rt53]
-
-[timA_lane0-3_rt53]: timA_lane0-3_rt53.png
-
-As you can see the signal has some jitter as every sample was taken in a
-different loop iteration. The result register only contains a single bit per
-lane.
-
-## Algorithm
-### Steps
-The algorithm finds the roundtrip time, IO delay and IO phase. The IO phase
-will be adjusted to match the falling edge of the preamble of each lane.
-The roundtrip time is adjusted to an minimal value, that still includes the
-preamble.
-
-### Synchronize to data phase
-
-The first measurement done in read-leveling samples all DQS values for one
-phase [0-64) * 1/64th DCK. It then searches for the middle of the low data
-symbol and adjusts timA to the found phase and thus the following measurements
-will be aligned to the low data symbol.
-The code assumes that the initial roundtrip time causes the measurement to be
-in the alternating pattern data phase.
-
-### Finding the preamble
-After adjusting the IO phase to the middle of one data symbol the preamble will
-be located. Unlike the data phase, which is an alternating pattern (010101...),
-the preamble consists of two high data cycles.
-
-The code decrements the IO delay/RTT and samples the DQS signal with timA
-untouched. As it has been positioned in the middle of the data symbol, it'll
-read as either "low" or "high".
-
-If it's "low" we are still in the data phase.
-If it's "high" we have found the preamble.
-
-The roundtrip time and IO delay will be adjusted until all lanes are aligned.
-The resulting IO delay is visible in the picture below.
-
-**roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs**
-![timA for lane0 - lane3, finding minimum roundtrip time][timA_lane0-3_discover_420x]
-
-[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png
-
-**Note: The sampled data has been shifted by timA. The preamble is now
-in phase.**
-
-## Fine adjustment
-
-As timA still points the middle of the data symbol an offset of 32 is added.
-It now points the falling edge of the preamble.
-The fine adjustment is to reduce errors introduced by jitter. The phase is
-adjusted from `timA - 25` to `timA + 25` and the DQS signal is sampled 100
-times. The fine adjustment finds the middle of each rising edge (it's actual
-the falling edge of the preamble) to get the final IO phase. You can see the
-result in the picture below.
-
-![timA for lane0 - lane3, fine adjustment][timA_lane0-3_adjust_fine]
-
-[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png
-
-Lanes 0 - 2 will be adjusted by a phase of -10, while lane 3 is already correct.
diff --git a/Documentation/Intel/NativeRaminit/timA_lane0-3_adjust_fine.png b/Documentation/Intel/NativeRaminit/timA_lane0-3_adjust_fine.png
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