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| author | Nico Huber <nico.huber@secunet.com> | 2018-05-04 14:28:46 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-08 03:01:04 +0000 |
| commit | 3de303179ac8db5104a77c0f36e3640623057052 (patch) | |
| tree | 18b7c91b4ef65639d17a5d04524eb205fa857be2 /Documentation/Intel | |
| parent | ea4d692d57b285382832e522a9ea06ca2d3a8759 (diff) | |
| download | coreboot-3de303179ac8db5104a77c0f36e3640623057052.tar.xz | |
{mb,nb,soc}: Remove references to pci_bus_default_ops()
pci_bus_default_ops() is the default anyway.
Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/Intel')
| -rw-r--r-- | Documentation/Intel/SoC/soc.html | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index d91166fd2c..b4804de221 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -456,7 +456,6 @@ Use the following steps to debug the call to TempRamInit: .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, }; </code></pre> </li> |