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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-08 19:50:09 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:25:45 +0000 |
| commit | 9d422ef3816234195714abae43e3c2d31098e059 (patch) | |
| tree | 3018c3fbeec3d242888d9b6edf217589fb7e19f1 /Documentation/Makefile.sphinx | |
| parent | d903fffbc9694ca228f60006d272c9cdde41e760 (diff) | |
| download | coreboot-9d422ef3816234195714abae43e3c2d31098e059.tar.xz | |
mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.
Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.
Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Makefile.sphinx')
0 files changed, 0 insertions, 0 deletions