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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-09-20 13:46:19 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-03 20:22:58 +0000 |
| commit | a9b5a393955d2731eb20e3312b95859a55d6230d (patch) | |
| tree | 00ffa99e0a7869465d86adde4904c09b4dcbc02e /Documentation/POSTCODES | |
| parent | 51bfc594bb619cc3f2964e53ee814d4bd14c0d5b (diff) | |
| download | coreboot-a9b5a393955d2731eb20e3312b95859a55d6230d.tar.xz | |
soc/intel/common/block: Update LPC lib
Add support for following functionality:
1. Set up PCH LPC interrupt routing.
2. Set up generic IO decoder range settings.
3. Enable CLKRUN_EN for power gating LPC.
Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/POSTCODES')
0 files changed, 0 insertions, 0 deletions