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| author | Xiang Wang <wxjstz@126.com> | 2019-06-14 11:16:13 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:28:56 +0000 |
| commit | 3d5bb2a5df7c16d0faa5e6e84b42f3220ccf8405 (patch) | |
| tree | b8833bcf3ad796276f57cfd856621e6eee1ac777 /Documentation/arch/riscv/index.md | |
| parent | b6d6739b4003ae315caa616639001e11dd0923f2 (diff) | |
| download | coreboot-3d5bb2a5df7c16d0faa5e6e84b42f3220ccf8405.tar.xz | |
Documentatioan: update stage handoff protocol
Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'Documentation/arch/riscv/index.md')
| -rw-r--r-- | Documentation/arch/riscv/index.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 888651dba6..9a5de34f09 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -15,7 +15,7 @@ Payloads run from the ramstage are started in S mode, and trap delegation will have been done. These payloads rely on the SBI and can not replace it. ## Stage handoff protocol -On entry to a stage or payload, +On entry to a stage or payload (including SELF payloads), * all harts are running. * A0 is the hart ID. * A1 is the pointer to the Flattened Device Tree (FDT). |