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authorPhilipp Hug <philipp@hug.cx>2018-10-29 21:32:51 +0100
committerRonald G. Minnich <rminnich@gmail.com>2018-10-30 02:09:05 +0000
commit1ed082bc8bfd557b80f620ff4bf7a98d39a3c7bc (patch)
tree4dffb0b366950f2dbe63c9ed0cce85402331bf42 /Documentation/arch/riscv/index.md
parentd4ab5bbc823b9d764b6f252b11e7b3ed03110d82 (diff)
downloadcoreboot-1ed082bc8bfd557b80f620ff4bf7a98d39a3c7bc.tar.xz
riscv: simplify timer interrupt handling
Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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