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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-09-14 08:27:50 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-09-15 12:43:26 +0000 |
| commit | c75f2d811933051c991d71f39aa94b43063ec479 (patch) | |
| tree | f6e5758df0203843ddb24b3c7d305582da276943 /Documentation/arch/riscv | |
| parent | ded91fffb833823ea7d71654c1e10696eba0d419 (diff) | |
| download | coreboot-c75f2d811933051c991d71f39aa94b43063ec479.tar.xz | |
arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706
There are 8 possible BERT context errors, with table ctx_names being a
table to print their names. Thus the table is supposed to have 8 elements,
and indeed it has 8 lines... but some lines are missing commas, and when
compiling it becomes a 5 element table. Add the commas at the appropriate
places.
BUG=b:115719190
TEST=none.
Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions