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| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2018-09-18 11:29:24 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-10-30 02:10:44 +0000 |
| commit | b06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1 (patch) | |
| tree | 7a40e00d1ce1f95368cf49aa2a121e12e08372df /Documentation/arch | |
| parent | 1ed082bc8bfd557b80f620ff4bf7a98d39a3c7bc (diff) | |
| download | coreboot-b06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1.tar.xz | |
Documentation/riscv: Improve `index.md`
1. Add dot/period to the end of sentences
2. Remove blank line at the end of the file
3. Break lines after 75 characters
4. Use RISC-V spelling
5. Add comma for clarity
Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28654
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch')
| -rw-r--r-- | Documentation/arch/riscv/index.md | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index c2ecaef958..888651dba6 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -1,6 +1,6 @@ -# RISCV architecture documentation +# RISC-V architecture documentation -This section contains documentation about coreboot on RISCV architecture. +This section contains documentation about coreboot on RISC-V architecture. ## Mode usage All stages run in M mode. @@ -17,7 +17,7 @@ will have been done. These payloads rely on the SBI and can not replace it. ## Stage handoff protocol On entry to a stage or payload, * all harts are running. -* A0 is the hart ID +* A0 is the hart ID. * A1 is the pointer to the Flattened Device Tree (FDT). ## Additional payload handoff requirements @@ -27,11 +27,12 @@ The location of cbmem should be placed in a node in the FDT. Traps are delegated in the ramstage. ## SMP within a stage -At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore. -At the end of the stage harts 1..max are released by changing the -semaphore. +At the beginning of each stage, all harts save 0 are spinning in a loop on +a semaphore. At the end of the stage harts 1..max are released by changing +the semaphore. -A possible way to do this is to have a pointer to a struct containing variables, e.g. +A possible way to do this is to have a pointer to a struct containing +variables, e.g. ```c struct blocker { @@ -39,9 +40,7 @@ struct blocker { } ``` -The hart blocks until fn is non-null, and then calls it. -If fn returns we will panic if possible, but behavior -is largely undefined. +The hart blocks until fn is non-null, and then calls it. If fn returns, we +will panic if possible, but behavior is largely undefined. Only hart 0 runs through most of the code in each stage. - |