diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2019-09-28 17:44:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-04 11:58:58 +0000 |
| commit | b1ef725f391b3864c5051c7e7290311c475cfcd3 (patch) | |
| tree | 0c79e4d7dce03eaeb64233075bde399498fb65b6 /Documentation/arch | |
| parent | 6f7c955464783ba21cda1bcf4b5582b2af0be31e (diff) | |
| download | coreboot-b1ef725f391b3864c5051c7e7290311c475cfcd3.tar.xz | |
cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.
Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.
Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.
Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.
The code can be easily ported to real hardware bootblock.
Tested on qemu q35.
Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'Documentation/arch')
| -rw-r--r-- | Documentation/arch/x86/index.md | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 73c982385a..462e7e6c6e 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -16,24 +16,36 @@ In order to add support for x86_64 the following assumptions are made: * The reference implementation is qemu * The CPU supports 1GiB hugepages -## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation -* 0-4GiB are identity mapped using 1GiB huge-pages +## Assuptions for all stages using the reference implementation +* 0-4GiB are identity mapped using 2MiB-pages as WB * Memory above 4GiB isn't accessible -* pagetables reside in _pagetables -* Romstage must install new pagetables in CBMEM after RAMINIT +* page tables reside in memory mapped ROM +* A stage can install new page tables in RAM -## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation -* Romstage installed pagetables according to memory layout -* Memory above 4GiB is accessible +## Page tables +Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes +the page tables to a file which is then included into the CBFS as file called +`pagetables`. + +To generate the static page tables it must know the physical address where to +place the file. + +The page tables contains the following structure: +* PML4E pointing to PDPE +* PDPE with *$n* entries each pointing to PDE +* *$n* PDEs with 512 entries each + +At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. ## Steps to add basic support for x86_64 * Add x86_64 toolchain support - *DONE* * Fix compilation errors - *DONE* * Fix linker errors - *TODO* -* Add x86_64 rmodule support - *ONGERRIT* +* Add x86_64 rmodule support - *DONE* * Add x86_64 exception handlers - *TODO* -* Setup page tables for long mode - *TODO* -* Add assembly code for long mode - *TODO* +* Setup page tables for long mode - *DONE* +* Add assembly code for long mode - *DONE* +* Add assembly code for postcar stage - *TODO* * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* |