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| author | Furquan Shaikh <furquan@google.com> | 2016-06-01 15:09:21 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-03 04:53:58 +0200 |
| commit | e3a692d7daf16d53764a4b0e30531491d4ae24bd (patch) | |
| tree | bedb6cd4b275ddc21d64926f36009a7cf6c150bf /Documentation/codeflow.svg | |
| parent | b54a2d1d76549fc6dfacb880439d8785a50a589f (diff) | |
| download | coreboot-e3a692d7daf16d53764a4b0e30531491d4ae24bd.tar.xz | |
intel/apollolake: Clear TSEG reg early in bootblock
TSEG register comes out of reset with a non-zero default value. This
causes issues when cbmem_top returns non-zero value based on TSEG read
before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
avoid unwanted side-effects.
Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15049
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'Documentation/codeflow.svg')
0 files changed, 0 insertions, 0 deletions