diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-24 13:43:22 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-07-30 16:55:08 +0000 |
| commit | 990a05d26123dc9bfa5e802ac66e1482d0c06f8a (patch) | |
| tree | c3f7623a69156a9649ac2845cb5a7c5998d6b2d6 /Documentation/contributing | |
| parent | 669e155ad2738c55e1bd52477a791afa682e23e9 (diff) | |
| download | coreboot-990a05d26123dc9bfa5e802ac66e1482d0c06f8a.tar.xz | |
soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform
chipset lockdown in ramstage.
BUG=b:138200201
TEST=FSP debug build suggests those UPDs are disable now.
Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation/contributing')
0 files changed, 0 insertions, 0 deletions