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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-08-30 20:54:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-01 05:15:05 +0000 |
| commit | d37ebddfd84699464d076642f35fce0ef21cd1d5 (patch) | |
| tree | a102e4567a55a5194636201b2fd59b8ee1e5442d /Documentation/corebootBuildingGuide.tex | |
| parent | c97b0607ff4883fc5ceab0da2c8687a91ece2d13 (diff) | |
| download | coreboot-d37ebddfd84699464d076642f35fce0ef21cd1d5.tar.xz | |
soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.
Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/corebootBuildingGuide.tex')
0 files changed, 0 insertions, 0 deletions