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| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-28 13:56:24 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-03 11:26:41 +0000 |
| commit | 73b1bd7992fb33f33c33747fd0919fc495c3d5c4 (patch) | |
| tree | 26f50ea0b5d47777e877210e03c85a22af64c4d9 /Documentation/coreboot_logo.png | |
| parent | 91e7fe7b547396857c7165a2c68aad5fda8730e4 (diff) | |
| download | coreboot-73b1bd7992fb33f33c33747fd0919fc495c3d5c4.tar.xz | |
soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.
BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb
Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'Documentation/coreboot_logo.png')
0 files changed, 0 insertions, 0 deletions