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authorNico Huber <nico.h@gmx.de>2016-11-27 14:43:12 +0100
committerNico Huber <nico.h@gmx.de>2016-11-28 17:37:48 +0100
commitd85a71a75c35b5bf683939e320ff7a501f89f583 (patch)
tree30f3e0306cb0de1367fe30ddd2d918df64bf4285 /Documentation/coreboot_logo.png
parent673a4d0f4d06bfb6556756c97300b4cea336d484 (diff)
downloadcoreboot-d85a71a75c35b5bf683939e320ff7a501f89f583.tar.xz
nb/intel/gm45: Fix panel-power-sequence clock divisor
We kept this value at it's default on the native graphics init path. Maybe the Video BIOS path, too, I don't know if the VBIOS sets it. The panel power sequencer uses the core display clock (CDCLK). It's based on the HPLLVCO and a frequency selection we made during raminit. The value written is the (actual divisor/2)-1 for a 100us timer. v2: Fix unaligned mmio access inherited from Linux. v3: Use MCHBAR8() instead. Also, the unaligned access might have worked after all. Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17619 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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