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| author | haridhar <haridhar.kalvala@intel.com> | 2015-12-04 10:41:23 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:19:25 +0100 |
| commit | f991bf071a52ecdc38f5c8e647683a33db0e26db (patch) | |
| tree | b96d5d64fc818567d712aabecf13d28edcb2e774 /Documentation/coreboot_logo.png | |
| parent | 425a4669485423d9a3de781f5c97765b9860a971 (diff) | |
| download | coreboot-f991bf071a52ecdc38f5c8e647683a33db0e26db.tar.xz | |
intel/skylake: Enable SaGv feature
This change enables SaGv feature for skylake
platform.As a result of this patch the skylake
platform will train memory at both low & high
frequency points.This will be used to
dynamically scale the work point
(voltage/frequencies).
The value "3" here means enable. Following
is the table for same.
0=Disabled(SaGv disabled)
1=FixedLow(Fixed to low frequency)
2=FixedHigh(Fixed to High frequency)
3=Enabled(SaGv Enabled.Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Tested on D1 silicon.
Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be
Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315806
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12997
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/coreboot_logo.png')
0 files changed, 0 insertions, 0 deletions