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author | Aaron Durbin <adurbin@chromium.org> | 2020-05-15 17:01:58 -0600 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-28 20:33:34 +0000 |
commit | ecbfa99f64c117f45dc6d1b0c50947f46daa3280 (patch) | |
tree | ad794077ca0876d901785f2c9cff12245daba256 /Documentation/hypertransport.svg | |
parent | 7729b29a589ca971a3122731ffc043039813279d (diff) | |
download | coreboot-ecbfa99f64c117f45dc6d1b0c50947f46daa3280.tar.xz |
drivers/intel/fsp2_0: add option to compress FSP-M in cbfs
Allow the ability for chipset or mainboard to choose to
compress FSP-M in cbfs using LZMA or LZ4 routines. However, only
non-XIP platforms will support FSP-M compression. Since the main
cbfs decompression paths are utilized add the appropriate checks
for including compression algorithms under the FSP-M compression
options.
On picasso FSP-M (debug builds) the following savings were measured:
no-compression:
fspm.bin 720896 none
FSP_COMPRESS_FSP_M_LZ4:
fspm.bin 138379 LZ4 (720896 decompressed) -80%
FSP_COMPRESS_FSP_M_LZMA:
fspm.bin 98921 LZMA (720896 decompressed) -86%
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'Documentation/hypertransport.svg')
0 files changed, 0 insertions, 0 deletions