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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-06-04 15:56:44 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-06-06 12:13:19 +0000
commit05284b64d00fbdcea9b7a163d4a9377bdb25d831 (patch)
treeddcb435503cbb68e87258c6ebb776e2b35c7a7a1 /Documentation/mainboard/hp/z220_sff.md
parentf97232236891bc8f5c816a96c98807a0f2449234 (diff)
downloadcoreboot-05284b64d00fbdcea9b7a163d4a9377bdb25d831.tar.xz
mb/hp: Add Z220 SFF workstation
* Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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+# HP Z220 SFF Workstation
+
+This page describes how to run coreboot on the [HP Z220 SFF Workstation] desktop
+from [HP].
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-------------+
+| Type | Value |
++=====================+=============+
+| Socketed flash | no |
++---------------------+-------------+
+| Model | N25Q128..3E |
++---------------------+-------------+
+| Size | 16 MiB |
++---------------------+-------------+
+| In circuit flashing | yes |
++---------------------+-------------+
+| Package | SOIC-16 |
++---------------------+-------------+
+| Write protection | No |
++---------------------+-------------+
+| Dual BIOS feature | No |
++---------------------+-------------+
+| Internal flashing | yes |
++---------------------+-------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge | bd82x6x |
++------------------+--------------------------------------------------+
+| CPU | model_206ax |
++------------------+--------------------------------------------------+
+| SuperIO | :doc:`../../superio/nuvoton/npcd378` |
++------------------+--------------------------------------------------+
+| EC | |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel ME |
++------------------+--------------------------------------------------+
+```
+
+[HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom