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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-20 01:44:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 14:53:08 +0000 |
| commit | e6e5ecb7e813fa151c558c739d5394dce0a2af8e (patch) | |
| tree | 5227024409ee0826db078d98aee3a61a1204c352 /Documentation/mainboard/lenovo/x1.md | |
| parent | 7bbe3bb9f0caf518af89bc18b99cd9ac32ceff3f (diff) | |
| download | coreboot-e6e5ecb7e813fa151c558c739d5394dce0a2af8e.tar.xz | |
sb/intel/i82801gx: Implement PCIe coalescing
The implementation is a simplified version of the haswell/broadwell
code. This also adds a chip option to enable coalescing from the
devicetree.
Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'Documentation/mainboard/lenovo/x1.md')
0 files changed, 0 insertions, 0 deletions