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authorPatrick Rudolph <siro@das-labor.org>2018-08-04 10:04:45 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-09-30 03:20:36 +0000
commit15d840558480536ddaca71bc1876254d59fca7fe (patch)
treeecbb8b330e53b9413eaf17a72e0fb79a9ed2523f /Documentation/mainboard/lenovo/xx30_series.md
parent3d1d966dd8866e8fd399f988b38b7ceba9f4cfee (diff)
downloadcoreboot-15d840558480536ddaca71bc1876254d59fca7fe.tar.xz
Documentation: Add basic flashing tutorial for Lenovo
* Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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+# Lenovo Ivy Bridge series
+
+## Flashing coreboot
+```eval_rst
++---------------------+--------------------------------+
+| Type | Value |
++=====================+================================+
+| Socketed flash | no |
++---------------------+--------------------------------+
+| Size | 8 MiB + 4MiB |
++---------------------+--------------------------------+
+| In circuit flashing | Yes |
++---------------------+--------------------------------+
+| Package | SOIC-8 |
++---------------------+--------------------------------+
+| Write protection | No |
++---------------------+--------------------------------+
+| Dual BIOS feature | No |
++---------------------+--------------------------------+
+| Internal flashing | Yes |
++---------------------+--------------------------------+
+```
+
+## Installation instructions
+* Update the EC firmware, as there's no support for EC updates in coreboot.
+* Do **NOT** accidently swap pins or power on the board while a SPI flasher
+ is connected. It will permanently brick your device.
+* It's recommended to only flash the BIOS region. In that case you don't
+ need to extract BLOBs from vendor firmware.
+ If you want to flash the whole chip, you need BLOBs when building
+ coreboot.
+* The *Flash layout* shows that by default 7MiB of space are available for
+ the use with coreboot.
+* In that case you only want to use a part of the BIOS region that must not
+ exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
+* ROM chip size should be set to 12MiB.
+
+```eval_rst
+Please also have a look at :doc:`../../flash_tutorial/index`.
+```
+
+## Splitting the coreboot.rom
+
+To split the coreboot.rom into two images (one for the 8MiB and one for the
+4 MiB flash IC), run the following commands:
+
+```bash
+dd of=top.rom bs=1M if=build/coreboot.rom skip=8
+dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
+```
+
+That gives one ROM for each flash IC, where *top.rom* is the upper part of the
+flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
+of the flash image, that resides on the 8 MiB flash.
+
+## Dumping a full ROM
+
+If you flash externally you need to read both flash chips to get two images
+(one for the 8MiB and one for the 4 MiB flash IC), and then run the following
+command to concatenate the files:
+
+```bash
+cat bottom.rom top.rom > firmware.rom
+```
+
+## Flash layout
+There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
+BIOS region. These two flash ICs appear as a single 12MiB when flashing
+internally.
+On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
+region. The update is then written into the EC once.
+
+![][fl]
+
+[fl]: flashlayout_xx30.svg
+