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author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-05-20 16:28:49 +0200 |
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committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-05-21 14:23:34 +0000 |
commit | b461865577ed57b4512c75e0becf44b6b7ed0922 (patch) | |
tree | 577fb97f3cab9e6215fb010811172231444d8784 /Documentation/mainboard/opencellular/rotundu.md | |
parent | b19de28c9889675125183f350e2a35f60e142562 (diff) | |
download | coreboot-b461865577ed57b4512c75e0becf44b6b7ed0922.tar.xz |
Documentation: Add Rotundu
Add information about flash and programming header.
Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'Documentation/mainboard/opencellular/rotundu.md')
-rw-r--r-- | Documentation/mainboard/opencellular/rotundu.md | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/Documentation/mainboard/opencellular/rotundu.md b/Documentation/mainboard/opencellular/rotundu.md new file mode 100644 index 0000000000..8773e960a3 --- /dev/null +++ b/Documentation/mainboard/opencellular/rotundu.md @@ -0,0 +1,76 @@ +# Rutundu + +This page describes how to run coreboot on the [Rotundu] compute board +from [OpenCellular]. + +## TODO + +* Configure UART +* EC interface + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q128 | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit. +Directly connecting a Pomona test-clip on the flash is also possible. + +**Closeup view of SOIC-8 flash IC** + +![][rotundu_flash] + +[rotundu_flash]: rotundu_flash.jpg + +**SPI header** + +![][rotundu_header2] + +[rotundu_header2]: rotundu_header2.jpg + +**SPI header pinout** + +Dediprog compatible pinout. + +![][rotundu_j16] + +[rotundu_j16]: rotundu_j16.png + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Baytrail | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[Rotundu]: https://github.com/Telecominfraproject/OpenCellular +[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/ +[flashrom]: https://flashrom.org/Flashrom |