mainboard: Add Clevo W650SZ

This port is based on the code generated with autoport with Haswell
support (30890).

It can boot Arch Linux from mSATA or USB with SeaBIOS payload.

The EHCI debug port is at the right hand side of the laptop, but the
debug message stops to display after mrc.bin initializes USB.

Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923
Signed-off-by: Iru Cai <mytbk920423@gmail.com>

3 files changed, 92 insertions, 0 deletions

diff --git a/Documentation/mainboard/clevo/w650sz.md b/Documentation/mainboard/clevo/w650sz.md
new file mode 100644
index 0000000000..037a4be3d3
--- /dev/null
+++ b/Documentation/mainboard/clevo/w650sz.md
@@ -0,0 +1,88 @@
+# Clevo W650SZ
+
+This page describes how to run coreboot on Clevo W650SZ.
+
+## Required proprietary blobs
+
+```eval_rst
+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
+```
+
+## Flashing coreboot
+
+### External programming
+
+Clevo W650SZ has two SOIC-8 flash chips. They're labeled "BIOS" and "ME"
+on the mainboard. The flash chip containing the BIOS is 4MB. It can be
+programmed with an SOIC-8 clip and a flash programmer (e.g. CH341a).
+
+Below is a picture of the flash chips on the mainboard.
+
+![W650SZ flash chips](w650sz_flash_chips.jpg)
+
+After building coreboot, you get a 6MB firmware image. You need to split
+out the 4MB BIOS region as follows, and flash to the 4MB chip.
+
+```bash
+dd if=build/coreboot.rom of=bios-4M.rom bs=1M skip=2
+```
+
+### Internal programming
+
+When coreboot is installed, you can do the internal flashing with flashrom.
+
+You need to unlock the IFD first. Read the 2MB chip, unlock the IFD using
+ifdtool as follows, then flash it back to the 2MB chip. In this example,
+the 2MB chip is read out as me.rom.
+
+```bash
+util/ifdtool -u me.rom
+```
+
+After IFD is unlocked, you can do the internal flashing as follows.
+
+```bash
+sudo flashrom -p internal:laptop=force_I_want_a_brick \
+   --ifd --image bios -w build/coreboot.rom
+```
+
+## Working
+
+- i7-4800MQ, 4G+4G, 8G+8G
+- initialisation with Haswell mrc version 1.6.1 build 2
+- integrated graphics
+- graphics init with libgfxinit
+- S3 suspend/resume
+- internal flashing under coreboot
+- Using `me_cleaner`
+- USB
+- Gigabit Ethernet
+- WLAN
+- SATA, mSATA
+- keyboard
+- touchpad
+- HDMI
+- VGA
+- audio
+- webcam
+
+## Not Working
+
+- EHCI debug: console message stops after mrc.bin initializes USB
+- EC ACPI (including battery and AC status)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/haswell/index`     |
++------------------+--------------------------------------------------+
+| Southbridge      | Intel Lynx Point (HM86)                          |
++------------------+--------------------------------------------------+
+| CPU              | Intel Haswell (FCPGA946)                         |
++------------------+--------------------------------------------------+
+| EC               | ITE IT8587E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
diff --git a/Documentation/mainboard/clevo/w650sz_flash_chips.jpg b/Documentation/mainboard/clevo/w650sz_flash_chips.jpg
new file mode 100644
index 0000000000..0894fb0590
--- /dev/null
+++ b/Documentation/mainboard/clevo/w650sz_flash_chips.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 8e88443ac3..c904c951ff 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -21,6 +21,10 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
 
+## Clevo
+
+- [W650SZ](clevo/w650sz.md)
+
 ## Emulation
 
 The boards in this section are not real mainboards, but emulators.