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| author | Subrata Banik <subrata.banik@intel.com> | 2018-11-26 15:43:18 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-28 11:50:19 +0000 |
| commit | 1c329a05de8b821cd85c25cf8ab7d1e73714073f (patch) | |
| tree | 01974040755006efe32807329471e17a703f9bf6 /Documentation/mainboard | |
| parent | 190e5bee4a75208d1975c639321f46d4425e3583 (diff) | |
| download | coreboot-1c329a05de8b821cd85c25cf8ab7d1e73714073f.tar.xz | |
soc/intel/icelake: Fix IO decode setup
Make pch_early_iorange_init() function similar to
soc/intel/cannonlake/bootblock/pch.c while fixing below issue:
* COM1 not being enabled properly.
TEST=Able to get serial output from an 8250IO UART device at
the standard 0x3f8 base address.
Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'Documentation/mainboard')
0 files changed, 0 insertions, 0 deletions