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authorTristan Corrick <tristan@corrick.kiwi>2019-01-06 22:04:27 +1300
committerPatrick Georgi <pgeorgi@google.com>2019-01-09 09:53:41 +0000
commit9747f886db384cb3d1c42dee93f33346dbd25806 (patch)
tree97f5303292e962ff052eb870a1be2fc3fef44519 /Documentation/mainboard
parent638dcf9a69423d161e742335ff595c431ba22f5d (diff)
downloadcoreboot-9747f886db384cb3d1c42dee93f33346dbd25806.tar.xz
Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed
The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Also add a link to the known issues for Haswell, which has some information on PCIe. Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/mainboard')
-rw-r--r--Documentation/mainboard/supermicro/x10slm-f.md10
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
index 8d03429ab6..2c2e6a84cd 100644
--- a/Documentation/mainboard/supermicro/x10slm-f.md
+++ b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -128,10 +128,6 @@ for caveats.
## Known issues
-- The x8 PCIe slots do not work, as the Haswell code is missing support.
- The code to support it has been written, but it still needs to be
- reviewed and merged.
-
- Broadwell CPUs are not supported. They might work with minimal changes
to the code, but this has not been tested.
@@ -144,10 +140,14 @@ for caveats.
in coreboot. The `coretemp` driver can still be used for accurate CPU
temperature readings from an OS, and hence the OS can do fan control.
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
+
## Untested
- TPM
-- PCIe x4 slot (it will almost certainly work)
+- PCIe (likely to work, but maybe not at Gen 3 speeds)
- BMC (IPMI) functionality
- internal serial port
- chassis intrusion header