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| author | Edward O'Callaghan <quasisec@google.com> | 2020-04-29 13:32:32 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-05-20 01:11:17 +0000 |
| commit | 64e15aac1b003ffde8db9969657a21f54f6c20f2 (patch) | |
| tree | 12db4fce2ea2ea9c47621ba468fd2a977b96746d /Documentation/northbridge | |
| parent | 66b9c0efb52f8953e52add59c70646fa1ce1b867 (diff) | |
| download | coreboot-64e15aac1b003ffde8db9969657a21f54f6c20f2.tar.xz | |
mb/google/hatch: Fix Puff variants rom size from 32768 -> 16384 KB
Originally variants make use of a 32MB chip whereas now they
use a 16MB SPI flash. Allow for the coordination of dealing
with the transition between phases.
V.2: Leave Puff alone at the moment due to the complexity of
coordination.
BUG=b:153682192
BRANCH=none
TEST=none
Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/northbridge')
0 files changed, 0 insertions, 0 deletions